Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS

TAN Ming; TANG Li-jun; HUANG Shui-long; XIE Hai-qing

Chinese

您当前的位置：

首页 >

文章列表页 >

Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS

更新时间：2026-09-04

- Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS
- Vol. 31, Issue 1, Pages: 156-159(2014)
- 作者机构：
  
  1. 1 长沙理工大学机构物理与电子科学学院,湖南,长沙,410004
  2. 2 中国科学院机构微电子研究所射频集成电路研究室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2014
- 稿件说明：
移动端阅览
谭茗, 唐立军, 黄水龙, 谢海情. 基于40nm CMOS工艺可快速锁定的宽带锁相环电路设计[J]. 微电子学与计算机, 2014, 31(1): 156-159.

TAN Ming, TANG Li-jun, HUANG Shui-long, et al. Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS[J]. 2014, 31(1): 156-159.
谭茗, 唐立军, 黄水龙, 谢海情. 基于40nm CMOS工艺可快速锁定的宽带锁相环电路设计[J]. 微电子学与计算机, 2014, 31(1): 156-159. DOI：

TAN Ming, TANG Li-jun, HUANG Shui-long, et al. Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS[J]. 2014, 31(1): 156-159. DOI：

摘要

通过改进鉴频鉴相器（PFD）的电路结构，增加一个控制模块自适应调整电荷泵的充放电电流大小，设计了一种可快速锁定的宽频带电荷泵锁相环电路.当鉴频鉴相器输出的相位误差值大于控制模块中的延迟时间τ时，打开控制开关增加电荷泵的电流，从而增加环路带宽，减少环路滤波器的电阻值，实现快速锁定，环路稳定性不变.当环路接近锁定时，调整带宽到预设的优化值，保证了系统性能的最优化.基于SMIC 40nm CMOS工艺，完成电路设计与仿真.结果表明：在电源电压为2.5 V时，该锁相环可实现输出频率范围为698~960 M Hz，1700~2200 MHz，2300~2700MHz，覆盖GSM，TD-SCDMA，WCDMA，TD-LTE四个通讯标准的工作频段，锁定时间小于12μs.

Abstract

Through improving the phase frequency discriminator circuit structure

and adding a control module to control charge pump current

a charge pump phase-locked loop circuit which has the characteristics of fast-lock and wide band has been designed.When the phase error value of the phase frequency discriminator is greater than the delay timeτ of the control module

the control switch is opened to increase the charge pump current

the loop bandwidth is increased

at the same time the resistance of the loop filter is reduced

realized fast lock

loop stability do not change.When the loop is close to lock

the bandwidth is adjusted to the presupposed optimization value to get a system of optimal characteristics.Based on SMIC 40 nm CMOS process

a phase-locked loop is designed

contain circuit and layout design.The results of simulation show:The output frequency covered GSM

TD-SCDMA

WCDMA

TD-LTE four communication standards working frequency band

in other words

the output frequency ranges for 698~960 M Hz

1 700~2 200 M Hz

2 300~2 700 M Hz with a setting time of less than 12μs at a 2.5 V supply.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

A low-temperature coefficient bandgap reference with high-order compensation structure

Design of a 56 Gb/s PAM-4 optical receiver front-end in 45 nm SOI CMOS

Design of a low jitter current mode self-biased phase-locked loop

A CMOS low-noise active down-conversion mixer

A low power CMOS current reference with process-insensitive temperature compensation

Related Author

WANG Bin

LI Haisong

YANG Yuxin

LIN Fujiang

ZHANG Wenjia

YIN Fei

LI Haisong

ZENG Yong

Related Institution

Xi'an Microelectronics Technology Institute

School of Microelectronics, University of Science and Technology of China

Institute of Electronic Science and Technology, University of Electronic Science and Technology

College of Communication Engineering, Chengdu University of Information Technology

Institute of Microelectronics of Chinese Academy of Science

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰