Design of a Self-biased High Efficiency CMOS UHF Recifier Circuit

DUAN Ji-hai; LUO Lei; WEI Bao-lin

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Design of a Self-biased High Efficiency CMOS UHF Recifier Circuit

更新时间：2026-09-04

- Design of a Self-biased High Efficiency CMOS UHF Recifier Circuit
- Vol. 31, Issue 1, Pages: 168-171(2014)
- 作者机构：
  
  桂林电子科技大学机构信息与通信学院,广西,桂林,541004
- 作者简介：
- 基金信息：
- DOI：
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- Published：2014
- 稿件说明：
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段吉海, 罗磊, 韦保林. 一种自偏置高效率CMOS超高频整流电路的设计[J]. 微电子学与计算机, 2014, 31(1): 168-171.

DUAN Ji-hai, LUO Lei, WEI Bao-lin. Design of a Self-biased High Efficiency CMOS UHF Recifier Circuit[J]. 2014, 31(1): 168-171.
段吉海, 罗磊, 韦保林. 一种自偏置高效率CMOS超高频整流电路的设计[J]. 微电子学与计算机, 2014, 31(1): 168-171. DOI：

DUAN Ji-hai, LUO Lei, WEI Bao-lin. Design of a Self-biased High Efficiency CMOS UHF Recifier Circuit[J]. 2014, 31(1): 168-171. DOI：

摘要

基于SMIC 0.18μm 1P6M标准CMOS工艺，设计并实现了一种低成本、高效率的超高频整流电路.该设计采用直流偏置电路和驱动电路对整流管的阈值电压进行补偿，消除了标准CMOS工艺阈值电压对整流电路效率的不利影响.在版图后仿真下，当输入915MHz，340mV的射频信号时，整流电路的输出电压为2.646V，启动时间为60μs，总体效率高达43.8%，整个电路版图面积为910μm ×600μm.

Abstract

A kind of ultra high frequency rectifier circuit with low cost

high efficiency is designed and realized based on the SMIC 0.18 μm 1P6M standard CMOS process in this paper

This design uses the dc bias circuit and drive circuit to compensate the threshold voltage of the rectifier

and eliminates the adverse effects of the standard CMOS technology threshold voltage on the rectifier circuit efficiency.With the post-layout simulation

when the input 915 M Hz

340 mV radio frequency signal

the rectifier circuit output voltage is 2.646 V

the start time is 60 μs

the overall efficiency is as high as 43.8%

the whole circuit layout area is 910 μm × 600 μm.

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