A L32 embedded processor

mainly used in the control field

is one of our self-developed CICS 32-bit processors.It is able to perform arithmetic and logic operations of 32-bit

16-bit

8-bit and 1-bit

and the threestage pipeline structure of which has been realized and verified by Verilog HDL.Based on this

a six-stage dynamic pipeline program is designed and implemented in this paper.By splitting the original adder which requires two clock cycles

into two stages

the computational speed of eight decimals has been improved.In this scheme

the former execution stage is divided into four stages according to the slowest instruction execution cycles.Since not all execution need to go through these four stages

this scheme not only realizes the parallel execution of instructions that need multiple clock cycles

but also finishes in a clock cycle for instructions that need only one clock.Through comprehensive verification of NC-verilog and waveform analysis of Debbusy

it is shown that the proposed method of six-stage dynamic pipeline enjoys a high throughput.