A Novel and High Performance SEU/SET-tolerant Latch Design

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A Novel and High Performance SEU/SET-tolerant Latch Design

更新时间：2026-09-04

- A Novel and High Performance SEU/SET-tolerant Latch Design
- Vol. 31, Issue 7, Pages: 27-31(2014)
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- Published：2014
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一种新颖高效抗SEU/SET锁存器设计[J]. 微电子学与计算机, 2014, 31(7): 27-31,36.

A Novel and High Performance SEU/SET-tolerant Latch Design[J]. 2014, 31(7): 27-31.
一种新颖高效抗SEU/SET锁存器设计[J]. 微电子学与计算机, 2014, 31(7): 27-31,36. DOI：

A Novel and High Performance SEU/SET-tolerant Latch Design[J]. 2014, 31(7): 27-31. DOI：

摘要

随着工艺技术的发展

集成电路对单粒子效应的敏感性不断增加

因而设计容忍单粒子效应的加固电路日益重要.提出了一种新颖的针对单粒子效应的加固锁存器设计

可以有效地缓解单粒子效应对于电路芯片的影响.该锁存器基于DICE和C单元的混合结构

并采用了双模冗余设计.SPICE仿真结果证实了它具有良好的抗SEU/SET性能

软错误率比M.Fazeli等人提出的反馈冗余锁存器结构减少了44.9%.与经典的三模冗余结构比较

面积开销减少了28.6%

功耗开销降低了超过47%.

Abstract

Along with the advance of process technology

the susceptibility of integrated circuit to single event effect has been increasing.Therefore

to design the circuits which can tolerate SEE become more and more important.This paper presents a novel harden latch which can mitigate the effect of SEE to IC chips.It is based on a mixed structure of DICE and C element

and utilizes the Dual Modular Redundancy (DMR) technology.Simulations using Hspice demonstrate that the structure proposed in this paper has a excellent performance to tolerate SEU/SET

and its soft error rate is 44.9% less than the feedback and redundant design proposed by M.Fazeli.Besides

compare to traditional Triple Modular Redundancy (TMR)

the proposed latch consumes about 28.6% less area

and more than47% power is saved.

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