Parity Detection Algorithm and VLSI Implementation Based on the RNS

ZHANG Yi-yun; ZHOU Wan-ting; LI Lei

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Parity Detection Algorithm and VLSI Implementation Based on the RNS

更新时间：2026-09-04

- Parity Detection Algorithm and VLSI Implementation Based on the RNS
- Vol. 31, Issue 3, Pages: 32-35(2014)
- 作者机构：
  
  电子科技大学电子科学技术研究院,四川,成都,610054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2014
- 稿件说明：
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张译匀, 周婉婷, 李磊. 一种基于余数系统的奇偶检测算法及VLSI实现[J]. 微电子学与计算机, 2014, 31(3): 32-35.

ZHANG Yi-yun, ZHOU Wan-ting, LI Lei. Parity Detection Algorithm and VLSI Implementation Based on the RNS[J]. 2014, 31(3): 32-35.
张译匀, 周婉婷, 李磊. 一种基于余数系统的奇偶检测算法及VLSI实现[J]. 微电子学与计算机, 2014, 31(3): 32-35. DOI：

ZHANG Yi-yun, ZHOU Wan-ting, LI Lei. Parity Detection Algorithm and VLSI Implementation Based on the RNS[J]. 2014, 31(3): 32-35. DOI：

摘要

提出了一种基于常用三模基{2+1，2-1，2+1}改进的奇偶检测算法，此方法仅使用一个位的模加器，一个+1位的进位选择加法器（CSA），一个2位的比较器及一些简单的组合单元即可实现，有效节省了资源，并简化了设计的复杂度.当=30时，面积仅为6130.958μm，延迟仅为0.67ns.

Abstract

A parity checker based on triple-mode{2+1

2-1

2+1}is proposed in this paper

this checker only need a bit adder

a +1 bit CSA adder

a 2 bit comparator and some simple combination unit

it lowers the resource consumption and simplifies the design effectively.When =30

an area of only 6130.958μm

the delay is only 0.67ns.

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