Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System

HU Sheng-ze; BAO Wei-dong

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Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System

更新时间：2026-09-04

- Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System
- Vol. 31, Issue 6, Pages: 30-35(2014)
- 作者机构：
  
  国防科学技术大学信息系统工程重点实验室,湖南,长沙,410073
- 作者简介：
- 基金信息：
- DOI：
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- Published：2014
- 稿件说明：
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胡升泽, 包卫东. 多通道信号并行采集和万兆高速传输系统设计[J]. 微电子学与计算机, 2014, 31(6): 30-35.

HU Sheng-ze, BAO Wei-dong. Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System[J]. 2014, 31(6): 30-35.
胡升泽, 包卫东. 多通道信号并行采集和万兆高速传输系统设计[J]. 微电子学与计算机, 2014, 31(6): 30-35. DOI：

HU Sheng-ze, BAO Wei-dong. Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System[J]. 2014, 31(6): 30-35. DOI：

摘要

给出了以高性能FPGA和DSP为核心实现的并行信号采集和万兆高速传输系统，通过5片ADC芯片的分时采集和误差校正实现了2.5 Gsps多通道信号高精度并行采集，基于交换路由芯片实现了万兆串行RapidIO互连.基于FPGA逻辑实现以Farrow结构分数延时滤波器为核心的定时误差校正算法；配置DSP高速串口、FPGA GTX收发器和路由芯片实现了可扩展的高速通信机制，优化实现了高性能DSP的信号处理.

Abstract

This paper presents an embedded Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System using TI TMS320C6455 DSP and Virtex5 FPGA

which can achieve 2.5 Gsps five-channel -time-interleaved Parallel Signal Acquisition and 10G RapidIO routing. The sample-timing error algorithm of signal reconstruction based Farrow filter is realized in FPGA

and by configure the high-speed serial port and the routing chip the high-speed communication mechanism can be extended. By analyzing the hardware architecture and resource of embedded platform

the efficient DSP-based compute is described.

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