Based on the belief propagation (BP) decoding algorithm

a high-speed partially parallel decoder architecture suited for quasi-cyclic low density parity check (QC_LDPC) codes is designed.It is applicable to all the QC_LDPC codes.In view of the traditional BP decoders have complex architecture

low system operating frequency and low throughput features

three improved methods are proposed.Firstly large number of complex function operations can be achieved through a look up table.Secondly

check nodes and variable nodes are all use 5-stage pipeline for processing.Last early termination strategy is adopted.This design can effectively reduce the complexity of the hardware implementation of the decoder

at the same time improve the frequency and the decode throughput of the system.