Pipelined IDCT/IDST VLSI Architecture for HEVC

YAO Zi-you; HE Wei-feng

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Pipelined IDCT/IDST VLSI Architecture for HEVC

更新时间：2026-09-04

- Pipelined IDCT/IDST VLSI Architecture for HEVC
- Vol. 31, Issue 9, Pages: 67-70(2014)
- 作者机构：
  
  上海交通大学微电子学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2014
- 稿件说明：
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姚子游, 何卫锋. 基于流水的HEVC IDCT/IDST模块VLSI设计[J]. 微电子学与计算机, 2014, 31(9): 67-70,75.

YAO Zi-you, HE Wei-feng. Pipelined IDCT/IDST VLSI Architecture for HEVC[J]. 2014, 31(9): 67-70.
姚子游, 何卫锋. 基于流水的HEVC IDCT/IDST模块VLSI设计[J]. 微电子学与计算机, 2014, 31(9): 67-70,75. DOI：

YAO Zi-you, HE Wei-feng. Pipelined IDCT/IDST VLSI Architecture for HEVC[J]. 2014, 31(9): 67-70. DOI：

摘要

2013年1月HEVC (High Efficient Video Coding)被ITU-T和ISO/IEC正式确立为新一代视频编码国际标准.为了实现更高的压缩效率

HEVC使用了多项新技术.在空间域变换方面

HEVC支持从4×4到32×32的可变尺寸的IDCT变换

同时根据模式进行4×4IDCT和IDST变换的选择.由此提出了一种HEVC IDCT/IDST变换架构.采用基于流水的数据流调度策略和系数矩阵优化方案

提升了硬件效率和接口带宽利用率.采用65nm工艺库综合后

一维IDCT/IDST单元的等效门数约为40K

最高工作频率为500MHz

与现有设计相比可以实现30%以上的硬件资源减少和60%以上的吞吐率效率提升.仿真结果显示该结构可以实现对4k×2k@30f/s视频的IDCT/IDST处理.

Abstract

The newest international video coding standard HEVC (High Efficiency Video Coding) is published by ITU-T and ISO/IEC in January

2013.To improve the compression efficiency

some new technologies have been adopted in HEVC.In spatial transform aspect

HEVC supports variable transform block sizes from 4×4 to 32×32 for IDCT as well as mode dependent 4×4IDST.In this paper

a novel IDCT/IDST architecture for HEVC is proposed.It uses pipelined data flow scheduling and coefficient matrix optimization to improve hardware efficiency and bandwidth utilization.Synthesized with 65 nm technology

the 1DIDCT/IDST is 40 K gate count and the maximum working frequency is 500 MHz.Compared with previous work

our architecture can get more than 30% reduction in hardware cost and 60% improvement in throughput efficiency.Experimental results show that it can deal with IDCT/IDST for 4k×2k@30f/s video sequence.

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