A Low-cost Zero-overhead In-circuit Debug System Design for SoC

HE Yong; WANG Teng; WANG Xin-an; PAN Bin

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A Low-cost Zero-overhead In-circuit Debug System Design for SoC

更新时间：2026-09-04

- A Low-cost Zero-overhead In-circuit Debug System Design for SoC
- Vol. 31, Issue 3, Pages: 89-93(2014)
- 作者机构：
  
  1. 1 北京大学深圳研究生院集成微系统实验室,广东,深圳,518055
  2. 2 西安科技大学机构电气与控制工程学院,陕西,西安,710054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2014
- 稿件说明：
移动端阅览
何勇, 王腾, 王新安, 潘滨. 一种低代价零开销SoC在线调试系统设计[J]. 微电子学与计算机, 2014, 31(3): 89-93.

HE Yong, WANG Teng, WANG Xin-an, et al. A Low-cost Zero-overhead In-circuit Debug System Design for SoC[J]. 2014, 31(3): 89-93.
何勇, 王腾, 王新安, 潘滨. 一种低代价零开销SoC在线调试系统设计[J]. 微电子学与计算机, 2014, 31(3): 89-93. DOI：

HE Yong, WANG Teng, WANG Xin-an, et al. A Low-cost Zero-overhead In-circuit Debug System Design for SoC[J]. 2014, 31(3): 89-93. DOI：

摘要

设计和开发嵌入式系统及应用，片上调试系统必不可少.针对自主设计的PKU-DSP II系统芯片，设计了基于串口通信的在线调试系统.片上调试模块在处理器内部调试数据通道和流水线管理单元的支持下，实现了软件/硬件断点、单步、复位和在线程序下载调试功能，还开发了上位机调试软件和图形界面.精确的流水线控制技术和流水线误停的处理，使得调试系统具有零时序开销的优点.FPGA原型验证结果表明设计功能正确，在不降低原有系统性能的前提下，增加调试功能后硬件资源增加小于3%.

Abstract

On-chip debug is essential for design and development of embedded systems and software.UART based in-circuit debug system is designed for our PKU-DSP II system-on-a-chip.With the assist of debug data channels and pipeline control unit within the processor

the on-chip debug module can support functions such as hardware/software breakpoint

single-stepping

system reset as well as online program downloading and debug software with GUI is developed for host computer.Accurate pipeline control technique and proper handling of pipeline mis-suspending provide the debug system the advantage of zero timing overhead.The FPGA prototyping results show that the proposed design is correct and the hardware cost increases by no more than 3% without reducing the performance of the system.

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