This paper designs a high-precision Sigma-Delta Digital-to-Analog Conver (Σ-ΔDAC)

to meet the data accuracy in wireless communication applications.The 64-time-oversampling interpolator consists of a half-band filter

a CIC filter and a sample-hold circuit

in which the half-band filter uses an improved implementation and saves the area consumption effectively.TheΣ-Δ modulator uses single-bit quantized single-loop 5th-order structure to reduce the sensitivity of the non-ideal characteristics of the analog parts.For the digital input signal with 400 kHz bandwidth and 1MHz sample rate

the simulated SNR is 113 dB and the Effective Number of Bits (ENOB) is 18 bits.