Aiming at the problem of low reliability in high speed data transmission over a long distance

this paper proposes a design that balanced reliability and high-speed transmission.The design is used LVDS as the high-speed transmission interfaces

FPGA as the logic control chip

the hardware circuit joined the equalization circuit and software program used positive and inverse codes as error control coding improve transmission reliability.The overall design scheme and the circuit module has carried on the detailed introduction and analysis

and has described the implementation of the program.Finally presents the design of the test results

also verify the transmission reliability of the design.