32 Bit Pipeline Multiplier Design Based on Booth Encoder

ZHAI Zhao-yue; HAN Zhi-gang

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32 Bit Pipeline Multiplier Design Based on Booth Encoder

更新时间：2026-09-04

- 32 Bit Pipeline Multiplier Design Based on Booth Encoder
- Vol. 31, Issue 3, Pages: 146-149(2014)
- 作者机构：
  
  同济大学电子科学与技术系,上海,201804
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2014
- 稿件说明：
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翟召岳, 韩志刚. 基于Booth算法的32位流水线型乘法器设计[J]. 微电子学与计算机, 2014, 31(3): 146-149.

ZHAI Zhao-yue, HAN Zhi-gang. 32 Bit Pipeline Multiplier Design Based on Booth Encoder[J]. 2014, 31(3): 146-149.
翟召岳, 韩志刚. 基于Booth算法的32位流水线型乘法器设计[J]. 微电子学与计算机, 2014, 31(3): 146-149. DOI：

ZHAI Zhao-yue, HAN Zhi-gang. 32 Bit Pipeline Multiplier Design Based on Booth Encoder[J]. 2014, 31(3): 146-149. DOI：

摘要

为了减少乘法指令在保留站中的等待时间，设计了一款32位流水线型乘法器，该乘法器将应用于作者设计的一款超标量处理器中.该乘法器应用了改进型的booth编码算法，对部分积生成电路进行了优化，并采用了4-2压缩器与3-2压缩器相结合的Wallace树型结构对部分积进行压缩，最后再根据各级的延迟，在电路中插入了流水线寄存器，使其运算速度得到了提高.该乘法器使用GSMC 0.18μm工艺进行综合.经过仿真验证，该乘法器大大减少了在保留站中等待执行的乘法指令的完成时间，使每个时钟周期都有一条新的乘法指令被发送至乘法器进行运算.

Abstract

In order to reduce the waiting time of the multiplication instructions in reservation

a 32-bit pipelined multiplier is designed in this paper.It will be applied to the design of a superscalar processor.In this design

a modified booth encoder is used and partial product generator circuit is optimized.The partial product is compressed by the combination with 4-2 compressor and 3-2 compressor in Wallace tree structure.At last

pipeline registers are inserted according to the delay of the several levels

which will accelerate computing speed.The multiplier is synthesized in GSMC 0.18μm process.According to simulation and verification

this multiplier reduce the complement time of the IR waiting to execute in reservation stations.A new multiplication is sent to multiplier to compute in every cycle.

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