Based on the theory of DES algorithm

the present study improves DES algorithm hardware design in the way of operation speed and security.The optimized design increases the executive speed of DES algorithm by 4times

and enhances the security of algorithm by adding a module of optional random clock.Simulation verification and synthesize are implemented on DES algorithm Verilog design.Optimized design achieve integrated consideration between chip area and performance

to realize high-speed and high security DES algorithm

satisfying advanced requirements of speed and security in the field of encryption IP core application.