For SoC architecture design and embedded software development needs

use transaction-level modeling method with SystemC to complete the design of SPARC V 8 based transaction-level SoC verification platform.To reduce the design complexity and improve the simulation speed

completing transaction level modeling of instruction accurate SPARC V8 processor based on interpretive-execution technology

using hierarchical channel mechanism in SystemC to design transaction level models of AMAB bus

interrupt controller

UART

timer etc.Using Mibench to verify function and simulation speed of the verification platform after completing building the transaction level SoC verification platform.The results show that its functionality is correct and its simulation speed has greatly improved compared with RTL SoC verification platform.