Design of DS/H Circuit for a Time-interleaved Pipelined ADC

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Design of DS/H Circuit for a Time-interleaved Pipelined ADC

更新时间：2026-09-04

- Design of DS/H Circuit for a Time-interleaved Pipelined ADC
- Vol. 31, Issue 4, Pages: 168-172(2014)
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- Published：2014
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时间交织流水线ADC的双采样保持电路设计[J]. 微电子学与计算机, 2014, 31(4): 168-172.

Design of DS/H Circuit for a Time-interleaved Pipelined ADC[J]. 2014, 31(4): 168-172.
时间交织流水线ADC的双采样保持电路设计[J]. 微电子学与计算机, 2014, 31(4): 168-172. DOI：

Design of DS/H Circuit for a Time-interleaved Pipelined ADC[J]. 2014, 31(4): 168-172. DOI：

摘要

基于SMIC 0.18μm，1.8V工艺，设计了一种新型的双采样保持电路，可用于12bit、100MHz采样频率的时间交织流水线（Pipelined） ADC中.设计了一种采用了增益增强技术并带有一种改进的开关电容共模反馈电路的全差分运放.并且针对该双采样保持电路设计了特定的时钟发生电路.在cadence电路设计平台中利用Spectre仿真，结果表明：该采样保持电路可以实现12位、100MS/s采样速率和15mW功耗，满足系统设计要求.

Abstract

This paper presents a new type of double sampling/holding circuit based on SMIC0.18 μm

1.8 V process.It can be used for 12 bit

100 M Hz sampling frequency

time interleaving pipeline ADC.Gain-boosted technique has been introduced and an modified switched capacitor common mode feedback circuit is attached to the amplifier in this paper.And for the double sampling and holding circuit

design specific clock generation circuit.Simulation has been run in Spectre under Cadence platform.The result shows that this circuit is specially used in a 12 bit

100 MHz sampling frequency high speed pipelined ADC and the power consumption is 15 mW

which meets the design requirement.

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