For the sake of improving the work efficiency of DSP

a 16-bit-fixed-point DSP core with four pipeline stages is presented in this paper. Considering the design of the whole system and key module of the DSP core

the specific method is given in the paper. Focused on the implementation of the pipeline and the instruction and data stream of the DSP core

the description of the complete design plan is eventually presented in this article. Finally

the instruction set of the DSP core is realized and verified with the utilization of Modelsim simulating environment. The results indicate that the DSP core can execute correctly all the instructions with maximum clock operation frequency of 12.5 MHz and complete high-speed algorithms within single machine cycle.