Design and Optimization of the 108-bit Leading Zero Counters Circuit

LI Yong; QIN Hai-yang; LI Zhen-tao

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Design and Optimization of the 108-bit Leading Zero Counters Circuit

更新时间：2026-09-04

- Design and Optimization of the 108-bit Leading Zero Counters Circuit
- Vol. 32, Issue 4, Pages: 1-4(2015)
- 作者机构：
  
  国防科学技术大学计算机学院,湖南,长沙,410073
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2015
- 稿件说明：
移动端阅览
李勇, 秦海阳, 李振涛. 108位前导0计数器的电路设计与优化[J]. 微电子学与计算机, 2015, 32(4): 1-4,9.

LI Yong, QIN Hai-yang, LI Zhen-tao. Design and Optimization of the 108-bit Leading Zero Counters Circuit[J]. 2015, 32(4): 1-4.
李勇, 秦海阳, 李振涛. 108位前导0计数器的电路设计与优化[J]. 微电子学与计算机, 2015, 32(4): 1-4,9. DOI：

LI Yong, QIN Hai-yang, LI Zhen-tao. Design and Optimization of the 108-bit Leading Zero Counters Circuit[J]. 2015, 32(4): 1-4. DOI：

摘要

采用2位分组进行并行分工计数

使用二叉树的电路结构进行108位前导0计数器电路设计.采用2位分组的108位前导0计数器电路进行PT分析的时序为0.17

而采用8位分组的RTL级代码进行DC综合的时序为0.21

通过比较发现设计电路在速度上比RTL级代码快了19%.

Abstract

This paper adopts 2-bit parallel packet to count respectively

108 leading zero counter circuit design uses the structure which is two binary tree. The timing that 108-bit leading zero counter using 2-bit packet which is analyzed by PT is 0.17

and the timing that the RTL code using 8-bit packet which is analyzed by DC is 0.21

Comparative experice tell us that the design circuit is 20% faster than the RTL code in speed.

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