Implementation of Pipeline Structure of SM3 Algorithm on FPGA

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- Implementation of Pipeline Structure of SM3 Algorithm on FPGA
- Vol. 32, Issue 1, Pages: 15-18(2015)
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- Published：2015
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SM3杂凑算法的流水线结构硬件实现[J]. 微电子学与计算机, 2015, 32(1): 15-18.

Implementation of Pipeline Structure of SM3 Algorithm on FPGA[J]. 2015, 32(1): 15-18.
SM3杂凑算法的流水线结构硬件实现[J]. 微电子学与计算机, 2015, 32(1): 15-18. DOI：

Implementation of Pipeline Structure of SM3 Algorithm on FPGA[J]. 2015, 32(1): 15-18. DOI：

提出一种流水线结构的硬件实现策略

同时采用CSA加法器进行关键路径压缩

极大地提高了工作频率和算法的计算速率.在191 MHz时钟频率下

实现了73.54 Gb/s的高吞吐率.

In this paper

we mainly introduce a hardware implementation based on pipeline structure method with a good performance. We improved the speed of per SM3

and the performance on FPGAs of Altera is about 49.6 to 66.5 times faster than others implementation of SM3.

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