In order to enhance processing efficiency and reduce hardware resource consumption of the extraction replacement and shift replacement in cipher algorithm

a high-speed reconfigurable extraction-shift hardware architecture based on iButterfly is constructed in this paper. At the same time

the generating routing information of framework are put forward

then mapping high-speed hardware is realized. Finally

the results show that the proposed extraction-shift units have high efficiency and flexibility. The number of 32-bit extraction-shift replacement operating frequency is 2 GHz under the CMOS 65 nm.