This paper presents a methodology and related mathematic model to characterize the process variation of individual MOS transistor by differential non-linearity (DNL). By measuring the output voltages and current values of output-driven MOS transistor among D/A converters in test chip which is fabricated by 90 nm/1.2 V CMOS process

the device mismatch factor ΔD which is used to describe the effect of process variation in the output-driven MOS transistors can be obtained. By formulating a quantitative mathematic model

the current mismatch caused by device variation as well as the output variation induced by this mismatch can be described accurately. Experimental results of DAC circuits proves that the characterization method we proposed is easy-to-use

as well provides theoretical basis and technique guidance for analog IC designer to predict circuit performance effectively.