The Independent Design of RISC Pipeline CPU

YUAN Ting; LIU Yi-jun

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The Independent Design of RISC Pipeline CPU

更新时间：2026-09-04

- The Independent Design of RISC Pipeline CPU
- Vol. 32, Issue 2, Pages: 124-128(2015)
- 作者机构：
  
  广东工业大学机构计算机学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2015
- 稿件说明：
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袁婷, 刘怡俊. 自主设计精简指令集的流水线CPU[J]. 微电子学与计算机, 2015, 32(2): 124-128.

YUAN Ting, LIU Yi-jun. The Independent Design of RISC Pipeline CPU[J]. 2015, 32(2): 124-128.
袁婷, 刘怡俊. 自主设计精简指令集的流水线CPU[J]. 微电子学与计算机, 2015, 32(2): 124-128. DOI：

YUAN Ting, LIU Yi-jun. The Independent Design of RISC Pipeline CPU[J]. 2015, 32(2): 124-128. DOI：

摘要

介绍了基于FPGA平台

设计16位精简指令集流水线CPU.该CPU参考MIPS架构设计精简指令集

通过分析指令处理过程实现五级流水线结构

结合"预测技术"和数据前推方法解决流水线相关问题.为了支持CPU软件架构

设计指令集的汇编编译器.在 Modelsim平台运行测试程序

给出仿真综合结果.通过试验结果对比表明

所设计的CPU处理过程所需时钟周期大大减少.

Abstract

This paper based on FPGA platform

designing a 16 bit pipelined RISC CPU core. With reference to the MIPS instruction set

CPU completing the design of RISC instruction set

realizing five stage pipelined structure by analyzing instruction processing

combined with the "prediction" and data forwarding method to solve the related problems of pipeline. To support the CPU software architecture

we design a compiler for the instruction set. In the Modelsim platform running test program

the simulation results are givenout. By comparing the experiment results

the clock cycles required is greatly reduced.

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