Wire-Length Driven Placement Algorithm for Antifuse FPGA

ZHANG Da-hua; LI Wei; DU Tao

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Wire-Length Driven Placement Algorithm for Antifuse FPGA

更新时间：2026-09-04

- Wire-Length Driven Placement Algorithm for Antifuse FPGA
- Vol. 32, Issue 3, Pages: 132-135(2015)
- 作者机构：
  
  电子科技大学电子薄膜与集成器件国家重点实验室机构,四川,成都,610054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2015
- 稿件说明：
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张大华, 李威, 杜涛. 反熔丝FPGA线长驱动布局算法[J]. 微电子学与计算机, 2015, 32(3): 132-135.

ZHANG Da-hua, LI Wei, DU Tao. Wire-Length Driven Placement Algorithm for Antifuse FPGA[J]. 2015, 32(3): 132-135.
张大华, 李威, 杜涛. 反熔丝FPGA线长驱动布局算法[J]. 微电子学与计算机, 2015, 32(3): 132-135. DOI：

ZHANG Da-hua, LI Wei, DU Tao. Wire-Length Driven Placement Algorithm for Antifuse FPGA[J]. 2015, 32(3): 132-135. DOI：

摘要

针对反熔丝FPGA的结构特点

提出了一种线长驱动的反熔丝FPGA布局算法.该算法基于VPR的模拟退火布局算法

针对反熔丝FPGA垂直布线资源有限的特点

提出了新型的成本函数并在CAD实验平台上予以实现.实验结果表明

与VPR布局算法相比

该方法不仅优化了线网总长度

使得线网总长度平均减少了12%

同时还减少了编程的通路反熔丝数目.

Abstract

A novel wire-length driven placement algorithm for antifuse FPGA is proposed based on the characteristics of the antifuse FPGA architecture. The proposed algorithm is based on the simulated annealing algorithm of VPR and takes the limited vertical routing resources of the antifuse FPGA into account. A new cost function is proposed and the algorithm is implemented on a CAD platform. The experimental results showed that compared to the placement results of VPR

the proposed algorithm not only improves the total wire length by 12% on average

but also reduces the number of programmed horizontal antifuses.

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Related Author

MAN Feng-huan

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Related Institution

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