Design and Application of High Speed Dual-Field Multiplier

ZHENG Zhao-xia; ZI Yi-chun; TIAN Yuan; WU Hao

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Design and Application of High Speed Dual-Field Multiplier

更新时间：2026-09-04

- Design and Application of High Speed Dual-Field Multiplier
- Vol. 33, Issue 5, Pages: 1-5(2016)
- 作者机构：
  
  华中科技大学光学与电子信息学院,湖北,武汉,430074
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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郑朝霞, 资义纯, 田园, 吴浩. 高速双域乘法器设计及其应用[J]. 微电子学与计算机, 2016, 33(5): 1-5.

ZHENG Zhao-xia, ZI Yi-chun, TIAN Yuan, et al. Design and Application of High Speed Dual-Field Multiplier[J]. 2016, 33(5): 1-5.
郑朝霞, 资义纯, 田园, 吴浩. 高速双域乘法器设计及其应用[J]. 微电子学与计算机, 2016, 33(5): 1-5. DOI：

ZHENG Zhao-xia, ZI Yi-chun, TIAN Yuan, et al. Design and Application of High Speed Dual-Field Multiplier[J]. 2016, 33(5): 1-5. DOI：

摘要

双域乘法器在椭圆曲线密码学中具有重要意义

是构成双域模乘器的重要组件.考虑到双域乘法器的关键路径主要由GF ()域决定; 因此

在传统的基4 Booth编码乘法器的基础上进行优化设计

改进部分积产生电路以及Wallace压缩电路

使其能够同时支持GF ()域和GF (2 )域.设计的双域乘法器在FPGA实现结果表明

双域乘法器比单独实现两个域面积减小16.9%;延时比单独的GF ()域增加1.188 ns.将设计的双域乘法器应用到模乘器

结果表明

该设计完成一次256 bit的模乘操作比已有的在时间上节约了7.35%.

Abstract

Dual-Field multiplier is the important component of Dual-Field Montgomery multiplier and has important meaning for elliptic curve cryptography. Considering that the critical path of Dual-Field multiplier depends on the GF() field

Partial product generating circuit and Wallace compressor circuit was optimized based on traditional radix-4 Booth encoder multiplier(GF()) to support both GF() and GF(2 ) field. The designed Dual-Field multiplier implemented on FPGA shows that the area is decreased by 16.9% compare to the separating implement. The delay is increased by 1.188 ns than the traditional field GF(). The designed Dual-Field multiplier is applied to Montgomery multiplier. The time for 256 bit Montgomery multiplier of our design is reduced by 7.35% than paper proposed.

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references

Swee K L S, Hiung L H. Performance comparison review of 32-bit multiplier designs[C]//Intelligent and Advanced Systems (ICIAS), 2012 4th International Conference on. Kuala Lumpur, IEEE, 2012(2): 836-841.

Tenca A F, Savas E, Koc C K. A design framework for scalable and unified multipliers in GF (p) and GF (2m)[J]. International Journal of Computer Research, 2004, 13(1): 68-83. DOI: 68

Satoh A, Takano K. A scalable dual-field elliptic curve cryptographic processor[J]. Computers, IEEE Transactions on, 2003, 52(4): 449-460. DOI: 449

Yeh W C, Jen C W. High-speed booth encoded parallel multiplier design[J]. Computers, IEEE Transactions on, 2000, 49(7): 692-701. DOI: 692

Ma W, Li S. A new high compression compressor for large multiplier[C]//Solid-State and Integrated-Circuit Technology, ICSICT 2008.9th International Conference on. Beijing, IEEE, 2008: 1877-1880.

史焱, 吴行军. 高速双有限域加密协处理器设计[J]. 微电子学与计算机, 2005, 22(5): 8-12. DOI: 8

郭晓, 蒋安平, 宗宇. SM2高速双域Montgomery模乘的硬件设计[J]. 微电子学与计算机, 2013, 30(9): 17-21. DOI: 17

刘建国, 张军, 杨晓辉, 等. 有限域模乘专用指令设计[J]. 计算机工程, 2011, 37(21): 105-107. DOI: 105

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