Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor

DU Yi-ran; LI Wei; DAI Zi-bin

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Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor

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- Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor
- Vol. 33, Issue 1, Pages: 10-14(2016)
- 作者机构：
  
  1. 解放军信息工程大学,河南,郑州,450002
  2. 复旦大学专用集成电路与系统国家重点实验室机构,上海,201203
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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杜怡然, 李伟, 戴紫彬. 多核密码处理器中的片上网络互连结构研究[J]. 微电子学与计算机, 2016, 33(1): 10-14.

DU Yi-ran, LI Wei, DAI Zi-bin. Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor[J]. 2016, 33(1): 10-14.
杜怡然, 李伟, 戴紫彬. 多核密码处理器中的片上网络互连结构研究[J]. 微电子学与计算机, 2016, 33(1): 10-14. DOI：

DU Yi-ran, LI Wei, DAI Zi-bin. Research and Implementation of Network-on-Chip Interlinkage Structure for Multi-core Cipher Processor[J]. 2016, 33(1): 10-14. DOI：

摘要

为有效解决目前单核密码处理器性能无法满足高速密码运算处理需求的问题

研究了片上网络结构的基本特点

设计并实现了基于共享存储式的簇状片上网络多核密码处理器架构

分析密码运算特征并完成密码算法的多核适配.与单核密码处理器性能相比

本架构有较强的并行性及可扩展性

能够更好地完成大位宽、细粒度密码算法的支持.高效的核间数据交互机制大大提升了片上网络多核密码处理器密码处理性能

能够实现最大426 Gb/s的网络数据吞吐量

与通用多核处理器实现密码算法相比

性能提升约5.7%~37.5%.

Abstract

In order to solve the problem that a single-core cipher processor cannot satisfy the high speed cryptographic operations demand

this paper focused on the network-on-chip architecture and proposed a new architecture based on shared memory for multi-core cipher processor. In the proposed architecture

this paper analyzed the characteristic of cryptographic operations and achieved a DES algorithm mapping. Comparing with the single-core cipher processor

the proposed architecture gets a better parallelism and expansibility

to provide a giant bandwidth and fine grit cryptographic algorithm support. An efficient data interaction mechanism is able to improve the performance of multi-core cipher processor

and achieved a maximum throughput for 426 Gb/s. The performance of the proposed architecture improved about 5.7%~37.5% when compared with the general purpose multi-core processor in achieving cryptographic algorithms.

关键词

Keywords

references

New York Sao Jie Chen, Lan Yingcherng. Reconfigurable networks-on-chip[M]. New York: Springer-Verlag, 2011.

Hu Weiwu, Zhang Yifu, Yang Liang, Godson-3B1500: A 32nm 1.35GHz 40w 172.8GFLOPS 8Core processor[C]// Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE Internationa. San Francisco, 2013: 54-55.

Jason Hart, Steve Butler, Hoyeol Cho, A 3.6GHz 16-Core SPARC SoC processor in 28nm[C]// Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. San Francisco, 2013: 48-49.

Ou Peng, Zhang Jiajie, Quan Heng. A 65nm39GOPS/W 24-Core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array[C]// Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. San Francisco, 2013: 56-57.

Ryuji Kan, Tomohiro Tanaka, Go Sugizaki. A 10th Generation 16-Core SPARC64 processor for mission_Critical UNIX server[C]// Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. San Francisco, 2013: 32-40.

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