Algorithmic Design and Implementation of A Three-Operand Leading-one Prediction Error-Correcting Code Module

WANG Jing-jing; FU Kun; CHENG Ting-ting; WEI Si-jie; GENG Yao-hua

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Algorithmic Design and Implementation of A Three-Operand Leading-one Prediction Error-Correcting Code Module

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- Algorithmic Design and Implementation of A Three-Operand Leading-one Prediction Error-Correcting Code Module
- Vol. 33, Issue 4, Pages: 10-15(2016)
- 作者机构：
  
  1. 河北工业大学计算机科学与软件学院,天津,300401
  2. 河北工业大学电气工程学院,天津,300401
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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王京京, 富坤, 程婷婷, 魏思捷, 耿跃华. 三操作数的前导1预测算法纠错编码模块的设计与实现[J]. 微电子学与计算机, 2016, 33(4): 10-15.

WANG Jing-jing, FU Kun, CHENG Ting-ting, et al. Algorithmic Design and Implementation of A Three-Operand Leading-one Prediction Error-Correcting Code Module[J]. 2016, 33(4): 10-15.
王京京, 富坤, 程婷婷, 魏思捷, 耿跃华. 三操作数的前导1预测算法纠错编码模块的设计与实现[J]. 微电子学与计算机, 2016, 33(4): 10-15. DOI：

WANG Jing-jing, FU Kun, CHENG Ting-ting, et al. Algorithmic Design and Implementation of A Three-Operand Leading-one Prediction Error-Correcting Code Module[J]. 2016, 33(4): 10-15. DOI：

摘要

针对三操作数预测算法中的预测误差

提出了纠错方案.依据前导1预测的流程以及预编码规则

设计了纠错模块的预编码规则

完成了其整体结构设计

采用硬件描述语言VHDL进行编程

并通过QuartusⅡ进行仿真验证

得到了相应的RTL级电路

最后对仿真结果进行了分析.仿真结果表明

设计完成的算法结构能够有效地完成前导1预测纠错的功能.

Abstract

In this paper

we propose an error correction scheme based on the prediction error of the three operation number prediction algorithm. According to the process of leading-one prediction and pre-encoding rules

designing a error-correcting module pre-encoding

and completing the overall structure of the error-correcting module

using hardware description language VHDL to program some function module to optimize the design process

and use QuartusⅡ tools to perform comprehensive validation

received the RTL-level hardware circuits

and last the results are analyzed and verified. Simulation results show that the designed algorithm structure can effectively complete the Leading-one prediction correcting function.

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Keywords

references

罗淑贞, 富坤, 高艳, 等. 基于FPGA的三操作数前导1预测算法的设计与性能分析[J]. 微电子学与计算机, 2015, 32(5): 16-20. DOI: 16

Vojin G Oklobdzija. An algorithmic and novel design of a leading zero detector circuit : Comparison with logic synthesis[J]. IEEE Transactions on VLSI Systems, 1994, 2(1): 124-128. DOI: 124

张峰. 128位浮点乘加融合部件的研究与实现[D]. 长沙: 国防科学技术大学, 2007.

Ji Rong, Ling Zhiqiang. Comments on "leading-oneprediction with concurrent positioncorrection"[J]. IEEE Transactions on Computers, 2009, 58(12): 1726-1727. DOI: 1726

P M Farmwald. On the design of high performance digital arithmetic units[D]. Palo Alto: Stanford University, 1981.

梅小露. 浮点乘加部件中三操作数前导1预测算法的设计[J]. 微电子学与计算机, 2005, 22(12): 41-45. DOI: 41

N T Quach. Reducing the lantency of floating-point arithmetic operations[D]. Palo Alto: Stanford University, 1994: 1-80.

Javuer D Bruguera, Tomas Lang. Leading-one prediction with concurrent position correction[J]. IEEE Transactions on Computers, 1999, 48(10): 1083-1097. DOI: 1083

李星. 前导1预测算法的设计与实现[J]. 计算机科学, 2013, 40(4): 31-33. DOI: 31

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