A Compiler Back-end for Multi-layer Heterogeneous Coarse-Grained Reconfigurable Architectures

LIU Yi-chao; ZHAO Zhong-yuan; SHENG Wei-guang; HE Wei-feng

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A Compiler Back-end for Multi-layer Heterogeneous Coarse-Grained Reconfigurable Architectures

更新时间：2026-09-04

- A Compiler Back-end for Multi-layer Heterogeneous Coarse-Grained Reconfigurable Architectures
- Vol. 33, Issue 8, Pages: 15-18(2016)
- 作者机构：
  
  上海交通大学微电子学院,上海,200240
- 作者简介：
- 基金信息：
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- Published：2016
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刘毅超, 赵仲元, 绳伟光, 何卫锋. 多层异构粗粒度可重构处理器的编译器后端设计[J]. 微电子学与计算机, 2016, 33(8): 15-18.

LIU Yi-chao, ZHAO Zhong-yuan, SHENG Wei-guang, et al. A Compiler Back-end for Multi-layer Heterogeneous Coarse-Grained Reconfigurable Architectures[J]. 2016, 33(8): 15-18.
刘毅超, 赵仲元, 绳伟光, 何卫锋. 多层异构粗粒度可重构处理器的编译器后端设计[J]. 微电子学与计算机, 2016, 33(8): 15-18. DOI：

LIU Yi-chao, ZHAO Zhong-yuan, SHENG Wei-guang, et al. A Compiler Back-end for Multi-layer Heterogeneous Coarse-Grained Reconfigurable Architectures[J]. 2016, 33(8): 15-18. DOI：

摘要

基于LLVM编译器平台

针对一种多层异构粗粒度可重构处理器

设计了完整的任务编译器后端模块.针对这种处理器独特的访存机制

提出了一种新的中间数据结构ConfigIR

使得编译器可以完成计算密集型任务在可重构阵列上的调度

最终生成并行配置信息.对相关计算密集型任务的性能进行测试

结果表明相对于串行执行

该编译器管理下的可重构架构可以获得2~3倍的加速.

Abstract

In this paper

we present a novel task compiler back-end based on LLVM compiler framework but targeting a kind of multi-layer heterogeneous CGRA. Aiming at the processor which has distinct way accessing memory

we propose a new data structure called ConfigIR

which can analyze computation intensive programs

schedule parallel tasks and generate configuration codes eventually. Experiment shows that several computation intensive algorithms can get twice or three times speed up than serial processing.

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Keywords

references

Koenig R, Bauer L, Stripf T, et al. KAHRISMA: a novel hypermorphic reconfigurable instruction-set multi-grained-array architecture[C]//Design, Automation Test in Europe Conf. Exhibition (DATE). Germary, 2010: 819-824.

Berlin Cardoso João M P, Hübner Michael. Reconfigurable computing: from FPGAs to hardware/software codesign[M]. Berlin, Springer, 2011.

Mei B, Vernalde S, Verkest D, et al. Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling[J]. Computers and Digital Techniques, 2003, 150(5): 255-261. DOI: 255

Zhu Min, Liu Leibo, Yin Shouyi, et al. A cycle-accurate simulator for a reconfigurable multi-media[J]. IEICE Trans. on Inf. % Syst., 2010, 93(12): 3202-3210. DOI: 3202

Yin Chongyong. Compiler framework for reconfigurable computing system[C]//ICCCAS 2009. International Conference on. USA, California, IEEE, 2009.

Stripf Timo. A compiler back-end for reconfigurable, mixed-ISA processors with clustered register files[C]//Parallel and distributed processing symposium workshops % PhD forum (IPDPSW), 2012 IEEE 26th International. China, Shanghai, IEEE, 2012.

Lattner C, Adve V. LLVM: a compilation framework for lifelong program analysis % transformation[C]//Proc. of Int'l Symposium on Code Generation and Optimization. USA, San Jose, 2004.

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