VLSI Design of 2D DST Architecture for HEVC

DU Gao-ming; GUO Chen-yang; ZHANG Duo-li; SONG Yu-kun

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VLSI Design of 2D DST Architecture for HEVC

更新时间：2026-09-04

- VLSI Design of 2D DST Architecture for HEVC
- Vol. 33, Issue 3, Pages: 20-24(2016)
- 作者机构：
  
  合肥工业大学微电子设计研究所,安徽,合肥,230009
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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杜高明, 郭晨阳, 张多利, 宋宇鲲. 基于HEVC整数DST的VLSI设计与实现[J]. 微电子学与计算机, 2016, 33(3): 20-24.

DU Gao-ming, GUO Chen-yang, ZHANG Duo-li, et al. VLSI Design of 2D DST Architecture for HEVC[J]. 2016, 33(3): 20-24.
杜高明, 郭晨阳, 张多利, 宋宇鲲. 基于HEVC整数DST的VLSI设计与实现[J]. 微电子学与计算机, 2016, 33(3): 20-24. DOI：

DU Gao-ming, GUO Chen-yang, ZHANG Duo-li, et al. VLSI Design of 2D DST Architecture for HEVC[J]. 2016, 33(3): 20-24. DOI：

摘要

为了提高帧内编码性能

HEVC(High Efficiency Video Coding)首次应用整数离散正弦变换(The discrete cosine transform

DST)模式.针对现有DST算法运用到硬件设计中存在的设计电路面积较大、运算速度较慢的问题

结合DST矩阵系数运算数值的特点

提出了一种新的DST算法.并以此算法为核心

设计出了对应的专用有符号乘法器

通过采用单端口输入输出和组合累加器的方法

提高了电路的运算速度以及降低了电路的工作面积.在SMIC 0.18 μm工艺下综合得到该电路最快工作频率为250 MHz

电路面积为358 940 μm.从仿真结果来看

该设计的2D-DST电路有效

并能够获得较为精简的电路.

Abstract

To improve the Intar coding performance

HEVC(High Efficiency Video Coding) is applied to Integer discrete sine transform for the first time. To solve the problem of that the DST algorithm applied to hardware design that can increase circult area and reduce operational speed

a new DST algorithm is proposed based on the characteristics of the DST matrix coefficients. And the special signal multiplier is designed by the new algorithm. To increase operational speed and to reduce circuit area

the circuit adopts the single-port input and output and the combination accumlation method. Using SMIC 0.18 μm technology

the proposed architecture is implemented with the maximum work frequency at 250 MHz and 358 940 μm circult area. From simulation result

this design is working and can get a streamline circult.

关键词

Keywords

references

Saxena A, Fernandes F C. CE7: Mode-dependent DCT/DST without 4*4 full matrix multiplication for intra prediction, ITU-T/ISO/IRCJCT-VC document JCTVC-E125[S]. Geneua, Switzerland, 2011.

Saxena A, Fernandes F C A, Reznik Y A. Fast transforms for Intra-prediction-based image and video coding[C]// Data Compression Conf. USA, Snowbird, Utah, 2013: 13-22.

Sung T, Shieh Y, Yu C, et al. High-efficiency and low-Power architectures for 2-D DCT and IDCT based on CORDIC rotation[C]//Proc. Int. Parallel Distrib. Comput. Appl. Technol. Taiwan, Taipei, 2006: 191-196.

Joshi R, Chen P, Marta. CE7: Mode-dependent intra residual coding, ITU-T/ISO/IEC JCT-VC document JCTVC-E098[S]. Geneua, Switzerland, 2011.

Rao K R, Kim D N, Wang J J. Fast fourier transform: algorithms and applications[M]. Berlin, Springer Verlag, 2010.

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