Engin Ipek, Onur Mutlu. Self-optimizing memory controllers: a reinforcement learning approach[C]//roceedings of the 35th Annual International Symposium on Computer Architecture. USA, Denver, 2008.

Onur Mutlu, Thomas Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors[C]//Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture. Dallas, 2007.

Briki A, Chavet C, Coussy P. A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller[C]//Signal Processing Systems (SiPS), 2013 IEEE Workshop on. Taiwan, Taipei, IEEE, 2013: 201-206.

Kanno Y, Mizuno H, Watanabe T. A DRAM system for consistently reducing CPU wait cycles[C]//VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on. Taiwan, Taipei, IEEE, 1999: 131-132.

Kyle J Nesbit, Nidhi Aggarwal. Fair queuing memory systems[C]//Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Hawaii, USA, 2006.

Yang C J, Liu H C, Ji K M, et al. Adaptive memory map switch for system on chip[C]//High Performance Computing and Communication % 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on. UK, Liverpool, IEEE, 2012: 1639-1642.

Manu Awasthi, David NellansHandling. The problems and opportunities posed by multiple on-chip memory controllers[C]//Proceedings of the 19th international conference on Parallel architectures and compilation techniques. Austria, Vienna, 2010.