An Architecture Design for Multiple Datasets Accumulation

HU Hao; HE Guang-hui

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An Architecture Design for Multiple Datasets Accumulation

更新时间：2026-09-04

- An Architecture Design for Multiple Datasets Accumulation
- Vol. 33, Issue 8, Pages: 19-23(2016)
- 作者机构：
  
  上海交通大学微电子学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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胡浩, 贺光辉. 一种多数据集混合累加电路设计[J]. 微电子学与计算机, 2016, 33(8): 19-23, 28.

HU Hao, HE Guang-hui. An Architecture Design for Multiple Datasets Accumulation[J]. 2016, 33(8): 19-23.
胡浩, 贺光辉. 一种多数据集混合累加电路设计[J]. 微电子学与计算机, 2016, 33(8): 19-23, 28. DOI：

HU Hao, HE Guang-hui. An Architecture Design for Multiple Datasets Accumulation[J]. 2016, 33(8): 19-23. DOI：

摘要

提出了一种包含输入缓存FIFO、加法器及其控制逻辑、存储单元三个部分的电流注入累加模块(Node Injected Current Accumulation

NICA)

解决了流水线阻塞大

控制逻辑复杂、累加混合的问题

并在此基础上采取分批处理的方式

减少了累加的延时

最终节省了硬件资源.在Virtex-7 690T开发板上综合布线后

得到了较好的硬件资源消耗结果

满足了EMTP系统的实时性仿真要求.

Abstract

This paper propose anNICA(Node Injected Current Accumulation) module consists of FIFO

adder with control logic and memory. We solve the problem of large blocking

complex control logic

hybrid accumulation. On this basis

with the method of batching

we reduce the delay

finally save the hardware resources. Using a Xilinx Virtex-7 FPGA as the target device

we implement our designs and present good performance.

关键词

Keywords

references

Chen Yuan, Venkata Dinavahi. Digital hardwareemulation of universal machine and universal line models for real-time electromagnetic transient simulation[J]. Industrial Electronics, IEEE Transactions on, 2012, 59(2): 1300-1309. DOI: 1300

Zhuo Ling, Gerald R Morris, Viktor K Prasanna. High-performance reduction circuits using deeply pipelined operators on FPGAs[J]. Parallel and Distributed Systems, IEEE Transactions on, 2007, 18(10): 1377-1392. DOI: 1377

Portland Hermann W Dommel. EMTP theory book[M]. Portland Bonneville Power Admin, 1985.

Zhuo Ling, Viktor K Prasanna. High-performance and area-efficient reduction circuits on FPGAs[C]//Computer Architecture and High Performance Computing, 2005. SBAC-PAD 2005. 17th International Symposium on. Brazil, IEEE, 2005.

Chen Y, Dinavahi V. FPGA-based real-time EMTP[J]. IEEE Transactions on Power Delivery, 2009, 24(2): 892-902. DOI: 892

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Related Institution

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