The Design of an Instruction Scheduler in a Simultaneous Multi-threaded Processor

LI Le; LI Tao

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The Design of an Instruction Scheduler in a Simultaneous Multi-threaded Processor

更新时间：2026-09-04

- The Design of an Instruction Scheduler in a Simultaneous Multi-threaded Processor
- Vol. 33, Issue 6, Pages: 27-31(2016)
- 作者机构：
  
  西安邮电大学机构电子工程学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
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李乐, 李涛. 同时多线程处理器的指令调度器设计[J]. 微电子学与计算机, 2016, 33(6): 27-31, 36.

LI Le, LI Tao. The Design of an Instruction Scheduler in a Simultaneous Multi-threaded Processor[J]. 2016, 33(6): 27-31.
李乐, 李涛. 同时多线程处理器的指令调度器设计[J]. 微电子学与计算机, 2016, 33(6): 27-31, 36. DOI：

LI Le, LI Tao. The Design of an Instruction Scheduler in a Simultaneous Multi-threaded Processor[J]. 2016, 33(6): 27-31. DOI：

摘要

同时多线程处理器SMT(Simultaneous Multi-Threading)是用于图形、图像及数字信号处理的一种可以实现指令级并行(ILP)和线程级并行(TLP)的轻核处理器.针对这种处理器提出了一种结构简单的动态指令调度器

用于避免四个活跃线程中指令间的结构冲突和对一些特殊指令的不同要求的调度.结果表明

SMT处理器中的指令调度器通过调度各线程的执行先后顺序

四个线程被选中的概率均接近25%.

Abstract

The simultaneous multithreaded processor is for graphics

image and digital signal processing and can be realized instruction-level parallelism(ILP) and thread-level parallelism(TLP) of light-core processors. The design of such a processor simple structure dynamic instruction scheduler is presented here for avoiding structural conflict between the four active threads instruction and some special instruction of the different requirements of scheduling. The results showed that

SMT processor instruction scheduler scheduled for execution by the order of each thread

four threads probability of being selected are close to 25%.

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references

Tullsen D M, Eggers S J, Levy H M. Simultaneous multithreading: maximizing on-chip parallelism[C]//22nd Annual International Symposium on Computer Architecture. USA, Berkeley, 1995

Eggers S J, Emer J S, Levy H M, et al. Simultaneous multithreading: a platform for next-generation processors[J]. IEEE Micro, 1997, 17(5): 12-19. DOI: 12

黄虎才. 多态阵列处理器的并行计算研究[M]. 西安: 西安邮电大学, 2014.

李涛, 肖灵芝. 面向图形和图像处理的轻核阵列机结构[J]. 西安邮电学院学报, 2012, 17(3): 41-47. DOI: 41

李涛, 杨婷, 易学渊. 萤火虫2: 一种多态并行机的硬件体系结构[J]. 计算机工程与科学, 2014, 12(2): 191-200. DOI: 191

李祖松, 许先超, 胡伟武, 等. 龙芯2号处理器的同时多线程设计[J]. 计算机学报, 2009, 32(11): 2266-2273. DOI: 2266

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