Design of a Region-Based Page Mapping Flash Translation Layer

CAI Xiao-le; ZHANG Ya-di; LI Ya-hui; HAI Yu-lin

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Design of a Region-Based Page Mapping Flash Translation Layer

更新时间：2026-09-04

- Design of a Region-Based Page Mapping Flash Translation Layer
- Vol. 33, Issue 4, Pages: 32-36(2016)
- 作者机构：
  
  1. 中航工业西安航空计算技术研究所,陕西,西安,710068
  2. 机载弹载计算机航空科技重点实验室,陕西,西安,710068
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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蔡晓乐, 张亚棣, 李亚晖, 海钰琳. 基于区域页级映射的闪存转换层设计[J]. 微电子学与计算机, 2016, 33(4): 32-36.

CAI Xiao-le, ZHANG Ya-di, LI Ya-hui, et al. Design of a Region-Based Page Mapping Flash Translation Layer[J]. 2016, 33(4): 32-36.
蔡晓乐, 张亚棣, 李亚晖, 海钰琳. 基于区域页级映射的闪存转换层设计[J]. 微电子学与计算机, 2016, 33(4): 32-36. DOI：

CAI Xiao-le, ZHANG Ya-di, LI Ya-hui, et al. Design of a Region-Based Page Mapping Flash Translation Layer[J]. 2016, 33(4): 32-36. DOI：

摘要

针对固态硬盘中闪存不能进行本地更新操作以及擦写次数有限的特性

基于多通道并行结构的固态盘

提出一种基于区域的页级地址映射方案

将连续逻辑页分配到不同的通道中并利用三级地址映射方法.利用动态和静态损耗均衡算法

提出了分层的损耗均衡算法和垃圾回收方案.分析表明该算法能释放固态盘内存空间

延长固态盘的寿命

提高整体性能

映射表内存占用相对传统页级映射减少近70%.

Abstract

In allusion to the shortcoming of lacking in-place write and the limited erasing operations of flash memory in SSD (Solid-State Drive)

this paper proposes a region-based page level address mapping algorithm considering the multi-channel architecture of SSD. The algorithm assigns continuous logical pages to different channels and imposes three-level address mapping method

besides

a scheme of hierarchical wear-leveling and garbage collection method is proposed in the basis of dynamic and static wear-leveling algorithm. Theoretical analysis shows that the algorithm we proposed can release memory space in SSD

prolong the life-span of SSD and improve the whole performance

the memory usage of mapping table can be decreased by nearly 70% compared with original page-level mapping method.

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references

Gupta A, Kim Y, Urgaonkar B. DFTL: A flash translation layer employing demand-based selective of page-level address mapping[J]. SIGPLAN Not., 2009, 44(3): 229-240. DOI: 229

Lee S W, Park D J, Chung T S, et al. A log buffer-based flash translation layer using fully-associative sector translation[J]. ACM Transactions on Embedded Computing Systems, 2007, 6 (3): 1-27. DOI: 1

Kang J, Kim J, Park C, et al. A mufti-channel architecture for high-performance and flash-based storage system[J]. Journal of Systems Architecture, 2007, 53: 644-658. DOI: 644

Hu Yang, Jiang Hong, Feng Dan, et al. Exploring and exploiting the multi-level parallelism inside SSDs for improved performance and endurance[J]. IEEE Transactions on Computers, 2013, 62(6): 1141-1155. DOI: 1141

Intel Corporation. Understanding the flash translation layer (FTL) specification[R]. Santa Clara: Intel Corporation, 1998.

Ban A. Flash file system optimized for page-mode flash technologies: USA, 5937425[P]. 1999-08-10.

Zhou You, Wu Fei, Huang Ping, et al. An efficient page-level FTL to optimize address translation in flash memory[C]//Proceedings of the Tenth European Conference on Computer Systems. New York: ACM, 2015: 12-27.

Kang J U, Jo H, Kim J S, et al. A superblock-based flash translation layer for nand flash memory[C]//Proceedings of the 6th ACM % IEEE International Conference on Embedded Software. New York: ACM, 2006: 161-170.

Kim J, Kim J M, Noh S H, et al. A space-efficient flash translation layer for compact-flash systems[J]. IEEE Transactions on Consumer Electronics, 2002, 48 (2): 366-375. DOI: 366

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