A real-time simulation platform based on hardware acceleration has been implemented since the simulation speed is too slow for complex integrated circuits. The codes which could be synthesized were downloaded to the hardware platform
while the other un-synthesizable ones were left running in simulation tools
and the data interaction between the hardware platform and the simulation tools is implemented by interface functions. The results of experiments indicate that the proposed platform
possessing fine flexibility and observability
can strongly heighten the simulation effort.
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references
Christopher Lavin, Marc Padilla, Jaren Lamprecht, et al. HMFlow: accelerating FPGA compilation with hard Macros for rapid prototyping[C] //Field-Programmable Custom Computing Machine(FCCM), 2011 IEEE 19th Annual International Symposium on. USA, Salt Lake City, 2011: 117-124.
田野. 基于FPGA的软硬件协同仿真平台的设计[D]. 黑龙江: 哈尔滨工业大学, 2010. .
SrivastavaR, Mudgil N, Gupta G, et al. SoC time to market improvement through device driver reuse: an industrial experience[C] //Electronic System Design(ISED), 2012 International Symposium on. India, 2012: 56-61.