Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration

LIU Wei; CHAI Zhen; ZHOU Hao-jie; WU Dong; CHAI Zhi-lei

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Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration

更新时间：2026-09-04

- Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration
- Vol. 33, Issue 8, Pages: 40-44(2016)
- 作者机构：
  
  1. 江南大学物联网工程学院,江苏,无锡,214122
  2. 数学工程与先进计算国家重点实验室,江苏,无锡,214125
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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刘伟, 柴镇, 周浩杰, 吴东, 柴志雷. FPGA运行时重构的延迟隐藏机制研究与实现[J]. 微电子学与计算机, 2016, 33(8): 40-44, 49.

LIU Wei, CHAI Zhen, ZHOU Hao-jie, et al. Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration[J]. 2016, 33(8): 40-44.
刘伟, 柴镇, 周浩杰, 吴东, 柴志雷. FPGA运行时重构的延迟隐藏机制研究与实现[J]. 微电子学与计算机, 2016, 33(8): 40-44, 49. DOI：

LIU Wei, CHAI Zhen, ZHOU Hao-jie, et al. Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration[J]. 2016, 33(8): 40-44. DOI：

摘要

设计并实现了一种FPGA运行时重构的延迟隐藏机制

通过在FPGA中进行页面管理、缓存架构设计、缓存策略研究

在多个任务运行时调度中

可以对用户隐藏BIT文件配置的延迟

提高了总体运行效率.从而使FPGA具备了和GPU一样的用户模式

为FPGA更广泛地用于计算领域提供了技术思路.

Abstract

This paper designs and realizes a delay hidden mechanism for FPGA runtime reconfiguration. Through the pages management of FPGA

the cache architecture design and caching policy research

the mechanism can hid the configuration delay of BIT file

improve the overall efficiency in the multiple tasks scheduling. It gives FPGA the same user mode with GPU

provides the idea of using FPGA in computing technology more widely.

关键词

Keywords

references

何宾. Xilinx FPGA设计权威指南[M]. 北京: 清华大学出版社, 2014.

Conger C, George A D, Gordon Ross A. Design framework for partial run-Time FPGA reconfiguration[C]//2008 International Conference on Engineerring of Reconfigurable Systems % Algorithms. Las Vegas, Nevada, USA, 2008.

Martin G, Smith G, High-level synthesis: past, present, and future[J]. IEEE Design and Test of Computers, 2009, 26(4): 18-25. DOI: 18

袁春兰, 熊宗龙, 周雪花, 等. 基于Sobel算子的图像边缘检测研究[J]. 激光与红外, 2009, 39(1): 85-87. DOI: 85

丁帅帅, 柴志雷. 基于HLS的SURF特征提取硬件加速单元设计与实现[J]. 微电子学与计算机, 2015, 32(9): 133-137. DOI: 133

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Related Institution

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