An impedance self-calibration circuit applying to high-speed serial interface receiver was studied and designed. It is used to reduce the signal reflection because of impedance mismatch of the receiver input channel and improve the signal integrity. Impedance self-calibration circuit using digital-analog hybrid negative feedback loop structure which is composed of comparator and impedance calibration unit. The impedance calibration unit is made up of finite-state machine and replication cell of the receiver resistor array

and the resistor array consist of 46 same resistor unit and one half-weight resistor unit with parallel hybrid. Simulation and verification indicates that the calibration precision of the impedance self-calibration circuit can reach to 3% and calibration range can reach to ±35%

when the frequency is 12.5 GHz the return loss is less than -15 dB. The chip was taped out in 55 nm CMOS technology

it occupied 218 m×133 m and the power consumption is 7.43 mW.