To deal with the low conversion precision of traditional ADC

a design of Σ-Δ ADC with 24-bit high conversion precision was introduced

and digital decimation filter of which was fabricated.The digital decimation filter consists of a controller

a seven stage CIC filter

a FIR compensation filter and a FIR decimation filter. Multi-stage variable decimation CIC filter with 8 output sample rate was proposed to fit different bandwidth signal.Pass band ripple of the combined filters was less than 0.05 dB

and the stop band attenuation was greater than 130 dB.Method of time division multiplexing between different channels was adopted to reduce more adders and multipliers than conventional time division multiplexing. Designed in SMICs 0.18-m CMOS process

the chip area was 0.81mmper channel.The circuit consumed only 18.26mW of power per channel when the output sample rate was 500 points per second.