ADPLL is the key component of modern communication system and computer interface circuits

and is applied in a large variety of situations. DCO is the most fundamental module in ADPLL

and influences the overall performance of it. A standard cell based DCO is proposed in this paper

in which the cascaded structure is used. The ladder shaped coarse-tuning stage can widen the operating range and save power consumption. Interpolation Circuits are adopted in the fine-tuning stage

and further improve frequency resolution to achieve a more accurate output clock. Simulation and verification are done about the DCO based on Tower Jazz 0.18um CMOS process. The results show that the DCO can operate under different corners and temperature

output clock signal of 200MHz with the frequency resolution of 10ps

and consume power up to 1.2 mw with high linearity and monotony. Moreover

the DCO can be totally designed by standard cells and implemented by digital flow

so has more portability and shorter turn-around time.