Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs

SHI Fang-xian; ZENG Li; WANG Miao; CAO Jian-xun; QUAN Miao-jing

Chinese

您当前的位置：

首页 >

文章列表页 >

Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs

更新时间：2026-09-04

- Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs
- Vol. 33, Issue 2, Pages: 64-68(2016)
- 作者机构：
  
  北京航空航天大学宇航学院,北京,100191
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
移动端阅览
史方显, 曾立, 王淼, 曹建勋, 权妙静. Flash型FPGA单粒子瞬态脉冲分段滤除电路设计[J]. 微电子学与计算机, 2016, 33(2): 64-68.

SHI Fang-xian, ZENG Li, WANG Miao, et al. Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs[J]. 2016, 33(2): 64-68.
史方显, 曾立, 王淼, 曹建勋, 权妙静. Flash型FPGA单粒子瞬态脉冲分段滤除电路设计[J]. 微电子学与计算机, 2016, 33(2): 64-68. DOI：

SHI Fang-xian, ZENG Li, WANG Miao, et al. Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs[J]. 2016, 33(2): 64-68. DOI：

摘要

为提高FPGA在辐射环境条件下的抗单粒子脉冲(SET)的能力

设计了一种由多个延时单元和并联逻辑保护单元(Guard Gate

GG)构成的SET脉冲分段滤除电路.将SET脉冲处理延时减小至传统方法的10.42%~49.8%

从而提高电路对SET脉冲的处理能力

同时占用的逻辑资源未有明显增加.

Abstract

A segmented filtering circuit with delay units and guard gates is proposed to filter SET pulses with different width

considering the range and distribution of SET pulse widths produced in FPGA and the propagation induced pulse broadening. Dividing the widths of SET pulses into several intervals

parallel guard gates with different delay buffers generate corresponding results to different intervals. According to the results

this circuit selects the output in the shortest time

improving the performance on dealing with SET pulses. Simulation results in Fusion family flash-based FPGA indicate that

compared to traditional methods

the segmented filtering circuit can cut the filtering delay of SET pulse in critical path down to 10.42%~49.8%

while power consumption decreasing and no hardware resource increase.

关键词

Keywords

references

梁斌, 陈书明, 刘必慰, 等. SET传播过程中的脉冲展宽效应[J]. 半导体学报, 2008, 29(9): 1827-1831. DOI: 1827

Lopez-Ongil C, Department E T, Madrid U C I D, et al. Logic masking for SET mitigation using approximate logic circuits[C]// On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International. Spain, Sitges, 2012, 7203(4): 176-181.

Kim J E, Lin J, McMurchie L, et al. Mitigation of single-and multiple-cycle-duration SETs using double-mode-redundancy (DMR) in time[C]// Aerospace Conference, 2005 IEEE. USA, Bigsky, 2005: 1-10.

Sterpone L, Battezzati N. On the mitigation of SET broadening effects in integrated circuits[C]//Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on. Austria, Vienna, IEEE, 2010: 36-39.

Battezzati N, Sterpone L, Ferlet-Cavrois V. Analysis of SET propagation in flash-based FPGAs by means of electrical pulse injection[C]//Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on. Belgium, Brugge, IEEE, 2009: 87-90.

黄晔. 同时针对SEU/SET/MBU的MOS集成电路抗辐射加固技术研究[D]. 上海: 上海交通大学, 2009.

费尔南达·利马·卡斯腾斯密得. 基于SRAM的FPGA容错技术[M]. 北京: 中国宇航出版社, 2009.

Wirth G, Kastensmidt F L, Ribeiro I. Single event transients in logic circuits-oad and poropagation induced pulse broadening[J]. Nuclear Science, IEEE Transactions on, 2008, 55(6): 2928-2935. DOI: 2928

Violante M. On the evaluation of radiation-induced transient faults in flash-based FPGAs[C]//On-Line Testing Symposium, IOLTS '08. 14th IEEE International. Greece, Rhodles, IEEE, 2008: 135-140.

Rezgui S, Wang J J, Tung E C, et al. New mjethodologies for SET characterization and mitigation in flash-based FPGAs[J]. Nuclear Science, IEEE Transactions on, 2007, 54(6): 2512-2524. DOI: 2512

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

A feature-oriented context understanding and slice analysis network for tuberculosis detection

Aerial small object detection algorithm based on improved RT-DETR

A review of large model development: technological evolution from BERT to Deepseek

Implementation and verification of a dual-chain power gating strategy for low power design

High gain stability high temperature operational amplifier based on reverse body bias

Related Author

No data

Related Institution

No data

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰