KASUMI algorithm is an encryption algorithm used in the third generation mobile communication system (3G). In this paper

we propose a two-in-one architecture to complete the design of KASUMI algorithm in chip. Based on the architecture

the iteration of the loop in KASUMI algorithm reduces from original 8 rounds to 4 rounds. Therefore

the number of clock cycles of the design is reduced and the throughput is improved. Additionally

the design still implements the encryption of f8 mode and the integrity verification of f9 mode. Using SMIC 0.13 m CMOS technology

clock frequency of this design and the count of the gates are 123.4 MHz and 13979gates respectively. Most importantly

the throughput achieves 1.97Gbps

which is 23% faster than previous results.