Research of Vertical Reuse Based on UVM

XIONG Tao; JIANG Jian-hua

Chinese

您当前的位置：

首页 >

文章列表页 >

Research of Vertical Reuse Based on UVM

更新时间：2026-09-04

- Research of Vertical Reuse Based on UVM
- Vol. 33, Issue 4, Pages: 64-68(2016)
- 作者机构：
  
  中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
移动端阅览
熊涛, 蒋见花. 基于UVM验证方法学的纵向可重用研究[J]. 微电子学与计算机, 2016, 33(4): 64-68.

XIONG Tao, JIANG Jian-hua. Research of Vertical Reuse Based on UVM[J]. 2016, 33(4): 64-68.
熊涛, 蒋见花. 基于UVM验证方法学的纵向可重用研究[J]. 微电子学与计算机, 2016, 33(4): 64-68. DOI：

XIONG Tao, JIANG Jian-hua. Research of Vertical Reuse Based on UVM[J]. 2016, 33(4): 64-68. DOI：

摘要

现在片上系统(SOC)的复杂度和集成度越来越高

这给验证带来了巨大的挑战.传统的验证方法存在各种不足

在效率方面已经远远达不到生产的要求.UVM是近年来兴起的一种高效的通用验证方法学

不仅可以缩短验证周期

而且具有很好的可重用性.UVM验证方法学的可重用主要分为横向的可重用和纵向的可重用

主要阐述了UVM中纵向可重用的方法

并以APB总线为例

描述了从模块级到系统级的验证平台的搭建方法

这种方法很好地体现了纵向重用提高验证效率的优势.

Abstract

As the complexity and size of SOC(System on chip)grow

verification of design faces huge challenge. There are many defects in the traditional verification so that it cant meet the demand of manufacture in the aspect of efficiency. UVM is a universal verification methodology which springs up in recent years and has high efficiency. It can not only shorten the period of verification

but also can be reused conveniently. The reuse of UVM mainly includes Horizontal reuse and Vertical reuse. This paper focuses on the Vertical reuse and takes the APB bus as example

to expatiate how to build a verification platform from module level to system level. The methodology obviously shows that the Vertical reuse has the advantage of improving verification efficiency.

关键词

Keywords

references

李博. 基于system verilog-vmm的仿真环境设计及其应用[D]. 哈尔滨: 哈尔滨工业大学, 2009: 3.

Drechsler R, Chevallaz C, Fummi F, et al, Panel: Future SoC verification methodology: UVM evolution or revolution[C]//Design, Automation and Test in Europe Conference and Exhibition (DATE). Dresden: DATE, 2014: 1-5.

Yun Young-Nam. Beyond UVM for practical SoC verification[C]//SoC Design Conference (ISOCC), 2011. Jeju: ISOCC, 2011: 158-162.

SalahK. A UVM-based smart functional verification platform: Concept, pros, cons, and opportunities[C]//Design % Test Symposium (IDT), 9th International. Dead Sea: IEEE, 2014: 94-99.

张强. UVM实战[M]. 北京: 机械工业出版社. 2014: 4. DOI: 4

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

An high hierarchical verification platform Based on UVM

The Implementation of Universal Verification Platform for Sub-model of DBF System Based on UVM

An UVM Based Mixed-signal Verification Environment

Research on assembly action recognition based on MSS-YOLO-MPHands fusion architecture

Aerial vehicle detection algorithm based on multi-scale fusion and small-object enhancement

Related Author

LI Chen-yang

SONG Shu-shen

WANG Tao

HUANG Chu-chao

DENG Qing-yong

ZHU Peng

XI Jian-bo

GENG Rui

Related Institution

Southwest China Institute of Electronic Technology

School of Computer Science and Technology,Dalian University of Technology

College of Engineering, University of Missouri

Digital Technology Center, No. 38 Research Institute, China Electronic Technology Group Corporation

Key Laboratory of Aperture Array and Space Application, No. 38 Research Institute, China Electronic Technology Group Corporation

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰