Analysis of Basic Methods and Prospect of 3D Microprocessor Design

YI Lei; SHAN Guang-bao; XIAO Jian-qing; LIU Song

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Analysis of Basic Methods and Prospect of 3D Microprocessor Design

更新时间：2026-09-04

- Analysis of Basic Methods and Prospect of 3D Microprocessor Design
- Vol. 33, Issue 8, Pages: 68-71(2016)
- 作者机构：
  
  西安微电子技术研究所,陕西,西安,710054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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怡磊, 单光宝, 肖建青, 刘松. 三维微处理器设计基本方法及前景分析[J]. 微电子学与计算机, 2016, 33(8): 68-71, 75.

YI Lei, SHAN Guang-bao, XIAO Jian-qing, et al. Analysis of Basic Methods and Prospect of 3D Microprocessor Design[J]. 2016, 33(8): 68-71.
怡磊, 单光宝, 肖建青, 刘松. 三维微处理器设计基本方法及前景分析[J]. 微电子学与计算机, 2016, 33(8): 68-71, 75. DOI：

YI Lei, SHAN Guang-bao, XIAO Jian-qing, et al. Analysis of Basic Methods and Prospect of 3D Microprocessor Design[J]. 2016, 33(8): 68-71. DOI：

摘要

介绍了三维处理器设计的基本内容

详细阐述了用于三维处理器中三维存储系统的设计方法及发展趋势

最后概括描述了目前三维处理器、三维存储系统设计中存在的问题

这将为国内三维处理器设计提供一定的借鉴.

Abstract

This paper introduces the fundamental contents of the three dimensional processor

describes the design methodology and development of the three dimensional storage system and discusses the development of the future development of three-dimensional processor. Finally

the paper concludes the existing problems in the design of 3D processors and 3D memory.

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Keywords

references

D O Son, H J Choi, H G Jeon, et al. Thermal-aware 3D Multi-core Process-or Design using Core and Level-2 Cache Placement[J]. International Journal of Control and Automation, 2013, 25(6): 25-28. DOI: 25

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Kim Y, Song Y H. Analysis of thermal behavior for 3D integration of DRAM[C]// Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on. Madrid Spain: IEEE, 2014: 1-2.

Azarkhish E, Loi I, Benini L. A high-performance multiported L2 memory IP for scalable three-dimensional integration[C]// 3D Systems Integration Conference (3DIC), 2013 IEEE International. San Francisco, California: IEEE, 2013: 1-8.

Guthmuller E, Miro-Panades I, Greiner A. Architectural exploration of a fine-grained 3D cache for high performance in a manycore context[C]// Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on. Istanbul: IEEE, 2013: 302-307.

Hsieh H C, Sun Y F, Yeh J C, et al. 3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system[C]// Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on. Italy: IEEE, 2014: 5012-5016.

Xie Y. Future memory and interconnect technologies[C]// Proceedings of the Conference on Design, Automation and Test in Europe EDA Consortium. San Jose: IEEE, 2013: 964-969.

Xie Y. Processor architecture design using 3D integration technology[C]//VLSI Design, 2010. VLSID'10. 23rd International Conference on. India: IEEE, 2010: 446-451.

Lefter M, Voicu G R, Cotofana S D. A shared polyhedral cache for 3D wide-I/O multi-core computing platforms[C]// Circuits and Systems (ISCAS), 2015 IEEE International Symposium on. Portuqal: IEEE, 2015: 425-428.

李丽, 张宇昂, 傅玉祥, 等. 三维众核片上处理器存储架构研究[J]. 南京大学学报(自然科学版), 2014, 50(3): 330-334. DOI: 330

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