Research of FPGA Timing Sequence Analysis Technology Based on Timing Sequence Path

ZHOU Shan; WANG Jin-bo; WANG Xiao-dan

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Research of FPGA Timing Sequence Analysis Technology Based on Timing Sequence Path

更新时间：2026-09-04

- Research of FPGA Timing Sequence Analysis Technology Based on Timing Sequence Path
- Vol. 33, Issue 1, Pages: 76-80(2016)
- 作者机构：
  
  中国科学院机构空间应用工程与技术中心,北京,100094
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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周珊, 王金波, 王晓丹. 基于时序路径的FPGA时序分析技术研究[J]. 微电子学与计算机, 2016, 33(1): 76-80.

ZHOU Shan, WANG Jin-bo, WANG Xiao-dan. Research of FPGA Timing Sequence Analysis Technology Based on Timing Sequence Path[J]. 2016, 33(1): 76-80.
周珊, 王金波, 王晓丹. 基于时序路径的FPGA时序分析技术研究[J]. 微电子学与计算机, 2016, 33(1): 76-80. DOI：

ZHOU Shan, WANG Jin-bo, WANG Xiao-dan. Research of FPGA Timing Sequence Analysis Technology Based on Timing Sequence Path[J]. 2016, 33(1): 76-80. DOI：

摘要

针对于航天高可靠FPGA测试时时序分析技术的重要性

根据多年FPGA设计测试经验对时序分析技术进行深入剖析

提炼出一套切实可行的时序分析技术

阐明了时序分析的分析对象

时序分析技术的主要方法

给出了时序分析时接口信号时序计算法则

以及时序测试结果的分析准则; 并把这套分析技术成功的应用到了多个航天高可靠软件的测试中

发现了很多由时序问题引起功能失效的重大问题

对其中常见的时序问题给予归类总结.

Abstract

For the significance of high reliable FPGA test timing sequence analysis technology on Spaceflight

depending on the FPGA design and test experience for several years

timing sequence analysis technology is analyzed deeply

and a set of feasible solution is extracted

and the analysis target of timing sequence analysis is clarified. The interface signal timing sequence calculation rules of timing sequence analysis and analysis rules of timing sequence test results are presented by the main method of timing sequence analysis technology; this set of technology is applied successfully on the tests of several high reliable software on Spaceflight

many significant functional disabled problems

caused by timing sequence problems

can be found

and the common timing sequence problems are classified and summarized.

关键词

Keywords

references

王石. 基于FPGA芯片的功能仿真平台构建及静态时序分析[D]. 西安: 西安电子科技大学, 2008.

王石. 基于LUT的FPGA时序分析及后仿真实现[D]. 西安: 西安电子科技大学, 2009.

鲍瑞. 芯片测试平台中的FPGA时序分析及芯片接口测试方法研究[D]. 广州: 华南理工大学, 2013.

周海斌. 静态时序分析在高速FPGA设计中的应用[J]. 电子工程师, 2005, 31(1): 41-44. DOI: 41

吕宗伟, 林争辉, 张镭. 数字集成电路的时序分析[J]. 微电子学, 2001, 31(2): 127-129. DOI: 127

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