Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS

CHEN Shi-tong; ZHAO Zhen-dong

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Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS

更新时间：2026-09-04

- Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS
- Vol. 33, Issue 4, Pages: 91-96(2016)
- 作者机构：
  
  哈尔滨工程大学自动化学院,黑龙江,哈尔滨,150001
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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陈世同, 赵振栋. 基于VHDL-AMS的流水线ADC结构式建模方法与仿真[J]. 微电子学与计算机, 2016, 33(4): 91-96.

CHEN Shi-tong, ZHAO Zhen-dong. Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS[J]. 2016, 33(4): 91-96.
陈世同, 赵振栋. 基于VHDL-AMS的流水线ADC结构式建模方法与仿真[J]. 微电子学与计算机, 2016, 33(4): 91-96. DOI：

CHEN Shi-tong, ZHAO Zhen-dong. Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS[J]. 2016, 33(4): 91-96. DOI：

摘要

目前很多模数转换器(ADC)缺乏仿真模型

为了大型模数混合信号系统建模与仿真的需要

提出一种基于VHDL模拟混合信号扩展(VHDL Analog and Mixed-Signal Extensions

VHDL-AMS)的流水线ADC结构式建模方法.以多比特位每级的12位分辨率、10 MSPS流水线ADC作为建模对象

根据流水线ADC的结构特征

在考虑非理想因素误差情况下

分别建立采样保持放大和乘法数模转换器的VHDL-AMS子模型

然后通过例化建立顶层流水线ADC的结构模型.通过SystemVision和Simulink联合仿真

得到静态性能参数微分非线性度和积分非线性度均小于1LSB

动态性能参数无杂散动态范围94.941 7dB

总谐波失真-94.941 9dB

信噪比58.754 4dB

验证了所提建模方法合的理与有效.

Abstract

A large amount of analog-to-digital converters(ADC)lack of simulation model now

a constructral modeling method for pipeline ADC using VHDL Analog and Mixed-Signal Extensions(VHDL-AMS)is proposed in this paper in order to meet the necessary of modeling and simulation of large analog/mixed signal system.Multi-bit/stage 12 bit

10 MSPS pipeline ADC is taken as modeling object

accroding to its architectural character

the VHDL-AMS sub-model of Sample-Hold Amplifier and Multiplying Digital to Analog Converter is built respectively with taking account of nonideal factors

and then the architectural model of high level pipeline ADC is built by instantiating.By the co-simulation of SystemVision and Simulink

intatic performance parameter Differential NonLinearity(DNL)and Integral Non-Linearity(INL)are all less than 1 LSB; dynamic performance parameter Spurious Free Dynamic Range(SFDR)is 94.9417 dB

Total Harmonic Distortion(THD)is-94.9419 dB

Signal to Noise Ratio(SNR)is 58.7544 dB.The result shows that the proposed modeling method is reasonable and verified.

关键词

Keywords

references

Lan D, Liu X D. Behavioral model based on simulink for 14-bit 200MS/s pipelined ADC[C]//International Conference on Control Engineering and Communi-cation Technology. Shenyang: IEEE, 2012: 79-82.

AMS Modeling Cookbook for VHDL-AMS. Mentor Graphics Corporation[R]. MentorGraphics Corporation, 2010.

薛亮. 10位高速流水线模数转换器的研究[D]. 北京: 清华大学, 2004: 42-50.

申振胜. 基于VHDL-AMS的ADC建模及仿真[D]. 西安: 西安电子科技大学, 2014.

Xu D J, Jun P. The study of code density histogram testing method to high-speed ADC based on DSP[C]//Proc of the 8th World Congress on Intellgent Control and Automation. Jinan: IEEE, 2010: 2069-2074.

IEEE-SA Standards Board. IEEE Std 1076.1-1999. Definition of analog and mixed signal extensions to IEEE Standard VHDL[S]. New York: The Institute of Electrical and Electronics Engineers, Inc, 1999.

Boston Mikael G, J Jacob Wikner, Tan N X N. CMOS data converters for communications[M]. Boston: Kluwer Academic Publishers, 2000.

刘蒲霞, 陆铁军, 王宗民. 16位流水线ADC系统级建模及仿真[J]. 微电子学与计算机, 2009, 26(12): 120-121. DOI: 120

孙可旭, 何乐年. 基于频域特性的流水线ADC数字校正技术[J]. 浙江大学学报: 工学版, 2013, 47(8): 1393-1301. DOI: 1393

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