An Improved Design of Proportional-Integral Digital Loop Filter

HU Jian-lai; LI Lei

Chinese

您当前的位置：

首页 >

文章列表页 >

An Improved Design of Proportional-Integral Digital Loop Filter

更新时间：2026-09-04

- An Improved Design of Proportional-Integral Digital Loop Filter
- Vol. 33, Issue 6, Pages: 92-94(2016)
- 作者机构：
  
  电子科技大学电子科学技术研究院,四川,成都,610054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
移动端阅览
胡建来, 李磊. 一种改进型比例积分环路滤波器的设计[J]. 微电子学与计算机, 2016, 33(6): 92-94, 99.

HU Jian-lai, LI Lei. An Improved Design of Proportional-Integral Digital Loop Filter[J]. 2016, 33(6): 92-94.
胡建来, 李磊. 一种改进型比例积分环路滤波器的设计[J]. 微电子学与计算机, 2016, 33(6): 92-94, 99. DOI：

HU Jian-lai, LI Lei. An Improved Design of Proportional-Integral Digital Loop Filter[J]. 2016, 33(6): 92-94. DOI：

摘要

为改善系统由于非线性Bang-Bang鉴相器的引入而导致的系统非线性

提出了一种改进型数字环路滤波器

能够根据相位误差的大小

自动调整环路系数

提高了系统线性度.在AMS数模混合电路仿真环境中

仿真了采用此环路滤波器的时钟数据恢复电路.仿真结果表明

相比于采用传统环路滤波器的时钟数据恢复电路

采用该结构的时钟数据恢复电路的线性度最高可提高60%.

Abstract

To improve the linearity of system using nonlinear Bang-Bang phase detector

this paper presents a proposed digital loop filter (DLF) with coefficients that adapt to relative magnitude of the phase error

improved system linearity. In AMS digital and analog simulation environment

clock and data recovery adopting the proposed DLF is simulated. The simulation results shows that the linearity of the clock and data recovery adopting proposed DLF increases by 60% at most compared to adopting conventional proportional-integral DLF.

关键词

Keywords

references

Ward S Titus, John G Kenney. A 5.6 GHz to 11.5 GHz DCO for digital dual loop CDRs[J]. IEEE Journal of solid-state circuits, 2012, 47(5): 1123-1130. DOI: 1123

刘阳. 基干数字锁相环的低功耗时钟发生器设计[D]. 北京: 北京交通大学, 2014.

GuanghuaShu, Saurabh Saxena, et al. A reference-less clock and data recovery circuit using phase-rotating phase-locked loop[J]. IEEE Journal of solid-state circuits, 2014, 49(4): 1036-1047. DOI: 1036

Habib Adrang, Hossein Miar-Naimi. Modeling of jitter inbang-bang CDR with Fourier Series Analysis[J]. IEEE Fransaction on Reyular Papers, 2013, 60(1): 3-10. DOI: 3

S Sidiropoulos, M A Horowitz. A semidigital dual delay-locked loop[J]. IEEE Journal of solid-state circuits, 1997, 32(11): 1683-1692. DOI: 1683

Liming Xiu, Wen Li, Meiners J, et al. A Novel All-Digital PLL With Software Adaptive Filter[J]. IEEE Journal of solid-state circuits, 2004, 39(3): 476-483. DOI: 476

杨莉荣, 王炜. 基于FPGA的数字锁相环设计[J]. 微计算机应用, 2009, 30(1): 68-71. DOI: 68

邓军勇, 蒋林, 曾泽沧. 高速CMOS时钟数据恢复电路的设计与仿真[J]. 微电子学与计算机, 2014, 31(11): 56-63. DOI: 56

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Microservices anomaly detection based on the correlation of monitoring metrics

Aerial small object detection algorithm based on improved RT-DETR

Implementation and verification of a dual-chain power gating strategy for low power design

Aerial vehicle detection algorithm based on multi-scale fusion and small-object enhancement

Steganography model guided by attention mechanism and improved dense convolution

Related Author

No data

Related Institution

No data

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰