Design of Low Energy Consumption 3-Input AND/XOR Gate

YANG Yuan; XIA Yin-shui; QIAN Li-bo

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Design of Low Energy Consumption 3-Input AND/XOR Gate

更新时间：2026-09-04

- Design of Low Energy Consumption 3-Input AND/XOR Gate
- Vol. 33, Issue 8, Pages: 102-106(2016)
- 作者机构：
  
  宁波大学机构电路与系统研究所,浙江,宁波,315211
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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阳媛, 夏银水, 钱利波. 低能耗三输入AND/XOR门的设计[J]. 微电子学与计算机, 2016, 33(8): 102-106.

YANG Yuan, XIA Yin-shui, QIAN Li-bo. Design of Low Energy Consumption 3-Input AND/XOR Gate[J]. 2016, 33(8): 102-106.
阳媛, 夏银水, 钱利波. 低能耗三输入AND/XOR门的设计[J]. 微电子学与计算机, 2016, 33(8): 102-106. DOI：

YANG Yuan, XIA Yin-shui, QIAN Li-bo. Design of Low Energy Consumption 3-Input AND/XOR Gate[J]. 2016, 33(8): 102-106. DOI：

摘要

提出了一种基于传输门逻辑的低能耗三输入AND/XOR门设计电路.基于55 nm CMOS工艺

采用HSPICE仿真软件在不同工艺角下对门电路进行后仿真分析

并与已有的AND/XOR门电路进行对比.仿真结果表明该电路的性能良好

在典型工艺角下

提出的电路的功耗、速度和功耗-延时积的改进量最高分别可达10.08%

29.03%与36.12%

满足低能耗的设计要求.

Abstract

A transmission gate logic based low energy consumption 3-input AND/XOR gate is proposed. Under 55 nm CMOS process

the post-simulations of the circuit under different process corners are carried out by using HSPICE and compared with the published circuits. The simulation results show that the performance of this circuit is good

under typical process corner

the improvement of the proposed circuit can be up to 10.08%

29.03% and 36.12% respectively in terms of the power

delay and power delay product

which meets the design requirement of low energy.

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references

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