Design of CDR Based on Behavioral Model Using Verilog-A and Matlab

XU Wei-lin; WU Di; WEI Xue-ming

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Design of CDR Based on Behavioral Model Using Verilog-A and Matlab

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- Design of CDR Based on Behavioral Model Using Verilog-A and Matlab
- Vol. 33, Issue 6, Pages: 104-108(2016)
- 作者机构：
  
  1. 桂林电子科技大学广西精密导航技术与应用重点实验室,广西,桂林,541004
  2. 桂林电子科技大学机构信息与通信学院,广西,桂林,541004
- 作者简介：
- 基金信息：
- DOI：
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- Published：2016
- 稿件说明：
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徐卫林, 吴迪, 韦雪明. 基于Verilog-A与Matlab的行为描述模型的CDR设计[J]. 微电子学与计算机, 2016, 33(6): 104-108.

XU Wei-lin, WU Di, WEI Xue-ming. Design of CDR Based on Behavioral Model Using Verilog-A and Matlab[J]. 2016, 33(6): 104-108.
徐卫林, 吴迪, 韦雪明. 基于Verilog-A与Matlab的行为描述模型的CDR设计[J]. 微电子学与计算机, 2016, 33(6): 104-108. DOI：

XU Wei-lin, WU Di, WEI Xue-ming. Design of CDR Based on Behavioral Model Using Verilog-A and Matlab[J]. 2016, 33(6): 104-108. DOI：

摘要

根据模拟集成电路系统级和行为级快速验证的需求

针对一种穿戴式超宽带射频接收前端的500 Mbps的时钟数据恢复电路(CDR)进行设计.传统CDR的Verilog-A模型一般是基于理想环路进行环路参数的分析

误差较大.利用Verilog-A与Matlab进行行为级建模时将电荷泵充放电电流的大小和时间不匹配等非理想因素考虑进来

并进行相位噪声的拟合.行为级和电路级的对比仿真验证了行为级模型的快速性和准确性

并对CDR电路级的设计具有前瞻性的指导意义.

Abstract

In accordance with the demand of fast verification of system level and behavioral level about analog integrated circuit

especially the 500 Mb/s clock and data recovery (CDR) circuit used in the receiver of UWB on-body network.The traditional CDR based on Verilog-A has been used to analyze the loop parameters with big random error in ideal condition.However

in this work

the non-ideal factors such as mismatch of magnitude and time between charge up and down current is proposed

which is also modeled by Verilog-A.Meanwhile

the total phase noise of the loop is synthesized by Matlab script.The comparison of circuit level and behavioral level verify the quickly and exactly characteristics of behavioral model

which means they have significant forward-looking directive meaning to circuit design of CDR.

关键词

Keywords

references

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S J Ahmed, D Orthner, T A Kwasniewski. Behaviovral test benches for digital clock and data recovery chircuits using verilog-A[C]//CICC 2005, San Jose, CA: IEEE, 2005: 297-300.

陈娟, 陈鑫. 适用于数字锁相环的快速建模方法[J]. 电子器件, 2012, 35(5): 535-539. DOI: 535

王颖. SerDes系统级设计及行为级验证[D]. 成都: 电子科技大学, 2012: 17-50.

M A Kossel, M L Schmatz. Jitter measurements of high-speed serial links[J]. IEEE Design and Test of Computers, 2004, 21(6): 536-543. DOI: 536

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