Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit

LI Heng; WANG Qin; JIANG Jian-fei

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Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit

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- Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit
- Vol. 33, Issue 7, Pages: 125-128(2016)
- 作者机构：
  
  上海交通大学微电子学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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李恒, 王琴, 蒋剑飞. 高精度SRAM端口时序参数测量电路的设计与实现[J]. 微电子学与计算机, 2016, 33(7): 125-128, 132.

LI Heng, WANG Qin, JIANG Jian-fei. Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit[J]. 2016, 33(7): 125-128.
李恒, 王琴, 蒋剑飞. 高精度SRAM端口时序参数测量电路的设计与实现[J]. 微电子学与计算机, 2016, 33(7): 125-128, 132. DOI：

LI Heng, WANG Qin, JIANG Jian-fei. Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit[J]. 2016, 33(7): 125-128. DOI：

摘要

对一种普通的数字时间转换器(Digital-to-Time Converter

DTC)进行了改进

能实现对输入信号延时的两级调节

一级粗调

一级精调

在SMIC 130nm工艺下

调节范围为0~2.0ns

调节精度达到5ps

同时减少了一半的面积

优化了结构的非线性误差.利用改进后的DTC结构

设计了两种测量方案

分别实现了对SRAM输入端口的建立时间、保持时间及输出端口的数据读取时间的测量.仿真结果表明

该电路对SRAM各个端口时序参数测量的误差小于3.33%.

Abstract

A common DTC(Digital-to-Time Converter)circuit structure has been optimized

it is able to achieve twostage adjustment levels

both coarse and specific level.With the SMIC 130 nm technology

the adjustment range of the DTC structure reaches 0 ~ 2.0ns and the resolution achieves 5ps.Meanwhile

the area of circuit is can be cut down by 50%

and non-linear error is optimized as well.Based on the improved DTC

two measuring schemes are designed to measure the setup time and hold time for input ports

and the data access time for output ports.The simulation result shows that the overall measurement error is less than 3.33%.

关键词

Keywords

references

Lee M K, Teng W K, Krishnasamy R K, et al. Delayline based embedded memory access time measurement: Circuit, implementation and characterization techniques[C]//Quality Electronic Design(ASQED), 2012 4th Asia Symposium on. Penang: IEEE, 2012: 259-264.

Robert Bogdan Staszewski, Sudheer Vemulapalli, porasant Vallur, et al. 1.3V20ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: express briefs, 2006, 53(3): 220-225. DOI: 220

Andreani P, Bigongiari F, Roncella R, et al. A digitally controlled shunt capacitor CMOS delay line[J]. Analog Integrated Circuits and Signal Processing, 1999, 18(1): 89-96. DOI: 89

Zhihong L, Yihao Z, Law H. Self-Calibrate two-step digital setup/hold time measurement[C]//VLSI Design Automation and Test(VLSI-DAT), 2010International Symposium on. Hsin Chu: IEEE, 2010: 232-235.

戴燕云, 沈继忠. Structure and design method for pulse-triggered flip-flops at switch level[J]. Journal of Central South University of Technology, 2010, 17(6): 1279-1284. DOI: 1279

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