TSV Array-Based 3D ICs Design Exploration and Optimization

WANG Tian-xi; JIANG Jian-fei; WANG Qin; MAO Zhi-gang

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TSV Array-Based 3D ICs Design Exploration and Optimization

更新时间：2026-09-04

- TSV Array-Based 3D ICs Design Exploration and Optimization
- Vol. 33, Issue 7, Pages: 129-132(2016)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
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- Published：2016
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王畑夕, 蒋剑飞, 王琴, 毛志刚. 基于TSV Array的三维集成电路优化设计研究[J]. 微电子学与计算机, 2016, 33(7): 129-132.

WANG Tian-xi, JIANG Jian-fei, WANG Qin, et al. TSV Array-Based 3D ICs Design Exploration and Optimization[J]. 2016, 33(7): 129-132.
王畑夕, 蒋剑飞, 王琴, 毛志刚. 基于TSV Array的三维集成电路优化设计研究[J]. 微电子学与计算机, 2016, 33(7): 129-132. DOI：

WANG Tian-xi, JIANG Jian-fei, WANG Qin, et al. TSV Array-Based 3D ICs Design Exploration and Optimization[J]. 2016, 33(7): 129-132. DOI：

摘要

通过在三维集成电路中使用TSV阵列

分析TSV阵列对于提高可靠性的同时给时序和布局布线等带来的负面影响.基于TSV阵列

完成三维集成电路后端流程设计和HEVC运动估计电路的三维实现.实验表明基于3×3 TSV阵列的三维集成电路

每个TSV阵列可以实现1个TSV的冗余

可靠性提高11.98%

功耗和布线上分别增加了19.6%和19.2%.

Abstract

This paper analysis TSV arrays positive effect on circuits reliability and negative effect on timing and wire length by complete the 3D circuit (HEVC motion estimation circuit) back-end design with it. Results of the research indicated that one TSV array could have one redundant TSV in a 3*3 TSV array

and the reliability improved 11.98%

power consumption and wire length increased 19.6% and 19.2%.

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references

Yao W, Shi F, He L, et al. Power-bandwidth trade-off on TSV array in 3D IC and TSV-RDL junction design challenges[C]// Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on. Tempe, AZ: IEEE, 2012: 79-82.

Meindl J D, Chen Q, Davis J A. Limits on silicon nanoelectronics for terascale integration[J]. Science, 2001, 293(5537): 2044-2049. DOI: 2044

Pang C, Wang Z, Ren X, et al. Electrical simulation of 3X3 TSV array with different signal and ground patterns[C]// Electronic Packaging Technology (ICEPT), 2013 14th International Conference on. Dalian: IEEE, 2013: 417-420.

Thorolfsson T, Gonsalves K, Franzon P D. Design automation for a 3DIC FFT processor for synthetic aperture radar: A case study[C]// Design Automation Conference46th ACM/IEEE. San Francisco, CA: IEEE, 2009: 51-56.

Zhao Y, Khursheed S, Al-Hashimi B M. Cost-effective TSV grouping for yield improvement of 3D-ICs[C]// 2012 IEEE 21st Asian Test Symposium IEEE. New Delhi: IEEE, 2011: 201-206.

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