Design of 900 V JTE Structure VDMOS Termination

SHI Cun-ming; FENG Quan-yuan; CHEN Xiao-pei

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Design of 900 V JTE Structure VDMOS Termination

更新时间：2026-09-04

- Design of 900 V JTE Structure VDMOS Termination
- Vol. 33, Issue 4, Pages: 129-132(2016)
- 作者机构：
  
  西南交通大学微电子研究所,四川,成都,610031
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
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石存明, 冯全源, 陈晓培. 一种900 V JTE结构VDMOS终端设计[J]. 微电子学与计算机, 2016, 33(4): 129-132.

SHI Cun-ming, FENG Quan-yuan, CHEN Xiao-pei. Design of 900 V JTE Structure VDMOS Termination[J]. 2016, 33(4): 129-132.
石存明, 冯全源, 陈晓培. 一种900 V JTE结构VDMOS终端设计[J]. 微电子学与计算机, 2016, 33(4): 129-132. DOI：

SHI Cun-ming, FENG Quan-yuan, CHEN Xiao-pei. Design of 900 V JTE Structure VDMOS Termination[J]. 2016, 33(4): 129-132. DOI：

摘要

垂直双扩散金属氧化物场效应晶体管(Vertical Double-diffused Metal-Oxide-Semiconductor Field Transistor

VDMOS)是由Pbody与外延层之间形成的PN结承受电压

由于工艺限制

元胞区域只能设计为突变结

而终端区域最常用的结构为场限环

在原理上也相当于突变结耐压.结合结终端扩展(Junction Termination Extension

JTE)技术

引入缓变结耐压

设计了一款900 V的终端结构

实现了992.0 V的仿真击穿电压

终端效率达到了98.6%

而且有效终端长度仅有130.2 m

在较大程度上减小了芯片的占用面积

提高了击穿电压

而且工艺流程与成熟的深阱场限环基本一致

有较好的兼容性.

Abstract

The breakdown voltage of Vertical Double-diffused Metal-Oxide-Semiconductor Field Transistor(VDMOS) is withstood by the PN junction form by Pbody and EPI. The cell region is designed as a abrupt junction because of the technique limitation.Field Limit Ring(FLR) is the most common structure used in termination region

and it can also take as a abrupt junction. In this paper

a 900 V termination structure is designed with the introduction of graded junction and the combination of Junction Termination Extension(JTE). The simulation breakdown voltage 992.0V with the effective termination length of only 130.2 m

and the efficiency is 98.6%. The chip area is significantly decreased

breakdown voltage is significantly increased

and the technique is the same to deep well FLRs

which means a good technique compatibility.

关键词

Keywords

references

张彦飞, 吴郁, 游雪兰, 等. 硅材料功率半导体器件结终端技术的新发展[J]. 电子器件, 2009, 32(3): 538-546. DOI: 538

Temple V A K. Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique[J]. IEEE Transactions on Electron Devices, 1983, 30(8): 954-957. DOI: 954

USA B Jayant Baliga. Fundamentals of power semiconductor devices[M]. USA: Springer, 2008.

陈星弼. 功率MOSFET与高压集成电路[M]. 南京市: 东南大学出版社, 1990.

吴克滂, 冯全源, 高晓蓉. 一款900 V VDMOS的VLD终端结构设计[J]. 电子元件与材料, 2015, 34(2): 43-46. DOI: 43

严向阳, 唐晓琦, 淮永进. 高压VDMOSFET击穿电压优化设计[J]. 纳米器件与技术, 2008, 45(10): 577-579. DOI: 577

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