A TSV Fault-Tolerance Method Based on Functional Segmentation

DU Gao-ming; CAO Shu-ting; ZHANG Duo-li; SONG Yu-kun; GAO Ming-lun

Chinese

您当前的位置：

首页 >

文章列表页 >

A TSV Fault-Tolerance Method Based on Functional Segmentation

更新时间：2026-09-04

- A TSV Fault-Tolerance Method Based on Functional Segmentation
- Vol. 33, Issue 5, Pages: 142-146(2016)
- 作者机构：
  
  合肥工业大学微电子所,安徽,合肥,230009
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
移动端阅览
杜高明, 曹舒婷, 张多利, 宋宇鲲, 高明伦. 基于功能细分的硅通孔容错方法[J]. 微电子学与计算机, 2016, 33(5): 142-146, 152.

DU Gao-ming, CAO Shu-ting, ZHANG Duo-li, et al. A TSV Fault-Tolerance Method Based on Functional Segmentation[J]. 2016, 33(5): 142-146.
杜高明, 曹舒婷, 张多利, 宋宇鲲, 高明伦. 基于功能细分的硅通孔容错方法[J]. 微电子学与计算机, 2016, 33(5): 142-146, 152. DOI：

DU Gao-ming, CAO Shu-ting, ZHANG Duo-li, et al. A TSV Fault-Tolerance Method Based on Functional Segmentation[J]. 2016, 33(5): 142-146. DOI：

摘要

硅通孔(Through Silicon Via

TSV)技术是现今主流的三维芯片上下层互联技术之一.将从三维片上网络(Network on Chip

NoC)垂直通道的功能细分入手: 按照TSV重要性的不同划分成组

对不同的TSV组配置不同的冗余配置比.在现有的"包-连接电路"(PCC)平台上完成的实验显示

该冗余容错方案保证了在TSV总数达到十万量级时

成品率依然高达99.999 99%的同时

面积开销与非功能细分方案相比优化了35%以上.

Abstract

Through Silicon Via (TSV) technology is the mainstream of interconnection technology on 3-D stacked chips

this article implements a fault-tolerance scheme based on functional segmentation for vertical channel on 3D-NoC chips: according to the difference of importance of TSVs

we divide these TSVs into groups and configure different redundant proportion. The relevant experiments on PCC platform have shown that the fault-tolerant scheme keeps the target yield of 99.9999% when the number of TSVs reaches hundred thousand of magnitude and reduces the area overhead compared with other schemes based on non-functional segmentation by 35%.

关键词

Keywords

references

Zhao Y, Khursheed S, Al-Hashimi B M. Online fault tolerance technique for TSV-Based 3-D-IC[J]. IEEE Transaction on Very Large Scale Integration Systems, 2014, 23(4): 1-1. DOI: 1

Rad M R N, Kourdy R, Nasab M R, et al. Improvement the NOC bandwidth and fault tolerant by multipath routing in three-dimensional topologies for multi-media applications[C]//Computer and Automation Engineering (ICCAE), 2010 The 2nd International Conference on. NY, USA: IEEE, 2010: 497-501.

Friedman E G. On-chip interconnect: The past, present, and future[C]//Proc of the Future Interconnects and Networks on Chip 1st NoC Workshop-DATE'06. [s. l. ]: IEEE, 2006.

Curran B, Ndip I, Guttovski S, et al. The impacts of dimensions and return current path geometry on coupling in single ended through silicon vias[C]//Proceedings of the 59th Intermation Conference on Electronic Components and Technology. Washington, DC, USA: IEEE, 2009: 1092-1097.

Zhang B, Agrawal V D. Diagnostic Tests for Pre Bond TSN Defects[C]//Proceedings of the 28th International Conference on VLSI Design. Bangalore: IEEE: 2015: 387-392.

Loi I, Angiolini F, Fujita S, et al. Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip[J]. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2011, 30(1): 124-134. DOI: 124

袁强, 赵振宇, 窦强, 等. 三维芯片中TSV链式冗余修复电路的设计与实现[J]. 计算机工程与科学, 2014, 36(5): 828-835. DOI: 828

王伟, 董福弟, 方芳, 等. 一种多链式结构的3D-SIC过硅通孔(TSV)容错方案[J]. 计算机工程与应用, 2012, 48(20): 75-80. DOI: 75

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Fault-tolerant neural network training framework based on client-server

Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips

Aerial vehicle detection algorithm based on multi-scale fusion and small-object enhancement

Design of ultra-low power real-time clock circuits

Simulation on the DC characteristics of double heterojunction p-GaN HEMT with AlN/GaN hybrid buffer layer

Related Author

He Meng

Xu Dawen

RUAN Hua-jie

GE Meng-ke

CHEN Song

Related Institution

School of Electronic Science & Applied Physics, Hefei University of Technology

University of Science and Technology of China

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰