Design and Implement of a Configurable PWM IP Core With Hardware Trigger Mechanism

WENG Chong-jie; XIONG Xiao-ming; MA De

Chinese

您当前的位置：

首页 >

文章列表页 >

Design and Implement of a Configurable PWM IP Core With Hardware Trigger Mechanism

更新时间：2026-09-04

- Design and Implement of a Configurable PWM IP Core With Hardware Trigger Mechanism
- Vol. 33, Issue 7, Pages: 154-158(2016)
- 作者机构：
  
  1. 广东工业大学机构自动化学院,广东,广州,510000
  2. 杭州电子科技大学机构微电子CAD所,浙江,杭州,310000
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2016
- 稿件说明：
移动端阅览
翁崇杰, 熊晓明, 马德. 一种可支持硬件触发机制的灵活可配PWM IP核的设计与实现[J]. 微电子学与计算机, 2016, 33(7): 154-158.

WENG Chong-jie, XIONG Xiao-ming, MA De. Design and Implement of a Configurable PWM IP Core With Hardware Trigger Mechanism[J]. 2016, 33(7): 154-158.
翁崇杰, 熊晓明, 马德. 一种可支持硬件触发机制的灵活可配PWM IP核的设计与实现[J]. 微电子学与计算机, 2016, 33(7): 154-158. DOI：

WENG Chong-jie, XIONG Xiao-ming, MA De. Design and Implement of a Configurable PWM IP Core With Hardware Trigger Mechanism[J]. 2016, 33(7): 154-158. DOI：

摘要

提出了一种具有高可配性、高实时性和较强适用性等特点的脉冲宽度调制IP核的设计.该PWM模块不仅可支持片上系统内硬件触发反馈机制

以加强片内IP核之间的互联性

而且还提供了模块内部资源共享的实现方案.仿真验证的结果表明: 此模块可支持多种输出模式

且其硬件触发的消耗时间比传统的软件触发的时间少了两倍多.因此

该模块可满足可配性高、适用性强和实时性高等设计需求

达到了设计预期的目的.

Abstract

A pulse width modulation (PWM) IP core that having the advantages in configuration

instantaneity and applicability is proposed in this paper. Not only does the PWM IP core support hardware trigger and feedback mechanism for enhancing interconnection among IP cores in the System-on-a-Chip (SoC)

but it can also offer a practical scheme with resource reuse inside the PWM IP core. Finally

according to comparative and analytical results of simulation and verification

they indicate that PWM IP core can support multiple output modes

and consuming time of hardware trigger is two times less than traditional software triggers by building environment of simulation

editing excitation of test and using tools of simulation. In conclusion

it can meet needs of different configuration

high instantaneity and efficient applicability for achieving designs aim.

关键词

Keywords

references

周悦. 基于SoC的IP软核设计与验证[D]. 西安: 西安电子科技大学, 2007.

史江义. 基于IP核的SOC设计关键技术研究[D]. 西安: 西安电子科技大学, 2007.

吴胜龙. 基于APB总线的通用PWM核设计与实现[D]. 济南: 山东大学, 2010.

候立刚. SOC芯片低功耗设计及功耗估计若干问题研究[D]. 北京: 北京工业大学, 2007.

Miguel A Sanchez, Marisa Lopez-Vallejo, Carlos A iglesias, et al. Improving hardware reuse through XML-based interface encapsulation[C]// 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems. Paris: IEEE, 2012: 49-56.

陈伟, 邹云屏, 耿攀. 三相PWM整流器的死区效应分析及补偿方法[J]. 高电压技术, 2009, 35(5): 1156-1163. DOI: 1156

邓清秀, 文小玲. 基于FPGA的三相PWM发生器的实现方法探讨[J]. 武汉化工学院学报, 2006, 28(1): 67-70. DOI: 67

胡海兵, 姚文熙, 江辉鸿, 等. 任意路通用PWM波形发生器的设计[J]. 电工技术学报, 2008, 23(12): 115-119. DOI: 115

宋延强, 刘川来, 李思昆, 等. SoC设计中的IP核复用技术研究[J]. 青岛化工学院学报, 2003, 23(3): 260-263. DOI: 260

曹阳, 李晓辉, 王力纬, 等. 基于AMBA总线的脉冲调制控制器IP核的设计与实现[J]. 武汉大学学报(理学版), 2007, 53(3): 369-274. DOI: 369

包明, 包奎. 实现PWM脉宽调制的FPGA芯片研制[J]. 电工技术, 2003, 23(6): 30-31. DOI: 30

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Monte carlo analysis of V-layout trench SiC neutron detector

A high-efficiency charge pump for ultra-low voltage boost systems

Microservices anomaly detection based on the correlation of monitoring metrics

Aerial vehicle detection algorithm based on multi-scale fusion and small-object enhancement

Design of ultra-low power real-time clock circuits

Related Author

No data

Related Institution

No data

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰